| Security and vulnerability implications of 3D ICs Y Xie, C Bao, C Serafy, T Lu, A Srivastava, M Tehranipoor IEEE Transactions on Multi-Scale Computing Systems 2 (2), 108-122, 2016 | 61 | 2016 |
| TSV-based 3-D ICs: Design methods and tools T Lu, C Serafy, Z Yang, SK Samal, SK Lim, A Srivastava IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 55 | 2017 |
| Detailed electrical and reliability study of tapered TSVs T Lu, A Srivastava 2013 IEEE international 3D systems integration conference (3DIC), 1-7, 2013 | 23 | 2013 |
| Modeling and layout optimization for tapered TSVs T Lu, A Srivastava IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015 | 19 | 2015 |
| Electromigration-aware placement for 3D-ICs T Lu, Z Yang, A Srivastava 2016 17th International Symposium on Quality Electronic Design (ISQED), 35-40, 2016 | 14 | 2016 |
| Gated low-power clock tree synthesis for 3D-ICs AS Tiantao Lu International Symposium on Low Power Electronics and Design, 319-322, 2014 | 13 | 2014 |
| Electrical-thermal-reliability co-design for TSV-based 3D-ICs T Lu, A Srivastava International Electronic Packaging Technical Conference and Exhibition 56888 …, 2015 | 8 | 2015 |
| Electromigration-aware clock tree synthesis for TSV-based 3D-ICs T Lu, A Srivastava Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 27-32, 2015 | 8 | 2015 |
| Phase-driven learning-based dynamic reliability management for multi-core processors Z Yang, C Serafy, T Lu, A Srivastava Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 7 | 2017 |
| Low-power clock tree synthesis for 3D-ICs T Lu, A Srivastava ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (3 …, 2017 | 7 | 2017 |
| Voltage noise induced DRAM soft error reduction technique for 3D-CPUs T Lu, C Serafy, Z Yang, A Srivastava Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 6 | 2016 |
| Post-placement optimization for thermal-induced mechanical stress reduction T Lu, Z Yang, A Srivastava 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 158-163, 2016 | 6 | 2016 |
| Enhanced Phase-Driven -Learning-Based DRM for Multicore Processors Z Yang, C Serafy, T Lu, A Srivastava IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 2 | 2018 |
| 3 Detailed Electrical T Lu, A Srivastava Physical Design for 3D Integrated Circuits, 39, 2017 | | 2017 |
| Physical design methodologies for low power and reliable 3D ICs T Lu University of Maryland, College Park, 2016 | | 2016 |
| Detailed electrical and reliability study of tapered TSVs AS Tiantao Lu IEEE 3D System Integration Conference, 2013 | | 2013 |
