| On the reliability of majority gates full adders W Ibrahim, V Beiu, MH Sulieman IEEE Transactions on nanotechnology 7 (1), 56-67, 2008 | 85 | 2008 |
| On single-electron technology full adders MH Sulieman, V Beiu IEEE Transactions on Nanotechnology 4 (6), 669-680, 2005 | 64 | 2005 |
| On Single Electron Technology Full Adders M Sulieman, V Beiu Nanotechnology 2004, IEEE-NANO 2004, 317-320, 2004 | 64 | 2004 |
| Characterization of a 16-bit threshold logic single-electron technology adder M Sulieman, V Beiu 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 34 | 2004 |
| Design and analysis of SET circuits: Using MATLAB modules and SIMON M Sulieman, V Beiu 4th IEEE Conference on Nanotechnology, 2004., 618-621, 2004 | 32 | 2004 |
| Low-power and highly reliable logic gates transistor-level optimizations MH Sulieman, V Beiu, W Ibrahim 10th IEEE International Conference on Nanotechnology, 254-257, 2010 | 26 | 2010 |
| Gate Failures Effectively Shape Multiplexing V Beiu, W Ibrahim, YA Alkhawwar, MH Sulieman IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems …, 2006 | 20 | 2006 |
| On practical multiplexing issues V Beiu, MH Sulieman 2006 Sixth IEEE Conference on Nanotechnology 1, 310-313, 2006 | 12 | 2006 |
| Threshold logic: from vacuum tubes to nanoelectronics V Beiu, JM Quintana, MJ Avedillo, M Sulieman 2003 46th Midwest Symposium on Circuits and Systems 2, 930-935, 2003 | 9 | 2003 |
| On the reliability of interconnected CMOS gates considering MOSFET threshold-voltage variations MH Sulieman International Conference on Nano-Networks, 251-258, 2009 | 5 | 2009 |
| Femto Joule Switching for Nano Electronics. V Beiu, J Nyathi, S Aunet, MH Sulieman AICCSA, 415-423, 2006 | 5 | 2006 |
| Threshold-voltage variations effects on the reliability of nano-scale CMOS logic gates MH Sulieman 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO), 744-747, 2009 | 4 | 2009 |
| Multiplexing Schemes in Single-Electron Technology MH Sulieman, V Beiu IEEE International Conference on Computer Systems and Applications, 424-428, 2006 | 4 | 2006 |
| Design and Analysis of Single-Electron Technology Neural-Inspired Gates and Arithmetic Circuits MH Sulieman PhD Thesis, Washington State University, 2004 | 4 | 2004 |
| Optimal Practical Adders using Perceptrons M Sulieman, V Beiu Proceedings of 2003 International Conference on Neural Networks and Signal …, 2003 | 3 | 2003 |
| Low-Power Reliable Nano Adders A Beg, M Sulieman, V Beiu, W Ibrahim Low-Power Reliable Nano Adders, 2017 | 2* | 2017 |
| Design and Simulation of 90 nm Threshold Logic Carry-Look-Ahead Adder T AlSalem, L Nazzal, M Samara, MH Sulieman 2019 International Arab Conference on Information Technology (ACIT), 283-286, 2019 | 1 | 2019 |
| On the Design of Nanoscale CMOS Threshold-Logic Adders MH Sulieman, ZFA Himat 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD …, 2018 | 1 | 2018 |
| Parallel Pipeline to ATM: Graphical Simulation Techniques M Sulieman, CH Ooi, M Fleury Proceedings of the Fifteenth Annual UK Performance Engineering Workshop …, 1999 | 1 | 1999 |
| Design and Simulation of a Nanoscale Threshold-Logic Multiplier MH Sulieman, M Mahmoud, R Raafat, G Reda TEM Journal 8 (2), 333, 2019 | | 2019 |
