| A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010 | 861 | 2010 |
| A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ... IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010 | 531 | 2010 |
| The 48-core SCC processor: the programmer's view TG Mattson, RF Van der Wijngaart, M Riepen, T Lehnig, P Brett, W Haas, ... SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010 | 364 | 2010 |
| RCKMPI–lightweight MPI implementation for Intel’s Single-chip Cloud Computer (SCC) IA Comprés Ureña, M Riepen, M Konow Recent Advances in the Message Passing Interface: 18th European MPI Users …, 2011 | 52* | 2011 |
| SCC: A flexible architecture for many-core platform research M Gries, U Hoffmann, M Konow, M Riepen Computing in Science & Engineering, 79-83, 2011 | 49 | 2011 |
| Invasive mpi on intel’s single-chip cloud computer IAC Ureña, M Riepen, M Konow, M Gerndt Architecture of Computing Systems–ARCS 2012: 25th International Conference …, 2012 | 13 | 2012 |
| Connecting the Cloud: Transparent and Flexible Communication for a Cluster of Intel SCCs. P Reble, C Clauss, M Riepen, S Lankes, T Bemmerl MARC@ RWTH, 13-19, 2012 | 7 | 2012 |
| Enabling computation intensive applications in battery-operated cyber-physical systems H Woithe, W Brozas, C Wills, B Pichai, U Kremer, M Eichhorn, M Riepen The 6th Many-core Applications Research Community (MARC) Symposium, 34-39, 2012 | 2 | 2012 |