| The contribution of low-energy protons to the total on-orbit SEU rate NA Dodds, MJ Martinez, PE Dodd, MR Shaneyfelt, FW Sexton, JD Black, ... IEEE Transactions on Nuclear Science 62 (6), 2440-2451, 2015 | 95 | 2015 |
| Impact of technology scaling on the combinational logic soft error rate NN Mahatme, NJ Gaspard, T Assis, S Jagannathan, I Chatterjee, ... 2014 IEEE international reliability physics symposium, 5F. 2.1-5F. 2.6, 2014 | 73 | 2014 |
| Frequency dependence of alpha-particle induced soft error rates of flip-flops in 40-nm CMOS technology S Jagannathan, TD Loveless, BL Bhuva, NJ Gaspard, N Mahatme, ... IEEE Transactions on Nuclear Science 59 (6), 2796-2802, 2012 | 65 | 2012 |
| Effects of threshold voltage variations on single-event upset response of sequential circuits at advanced technology nodes H Zhang, H Jiang, TR Assis, NN Mahatme, B Narasimham, LW Massengill, ... IEEE Transactions on Nuclear Science 64 (1), 457-463, 2016 | 40 | 2016 |
| Angular effects of heavy-ion strikes on single-event upset response of flip-flop designs in 16-nm bulk FinFET technology H Zhang, H Jiang, TR Assis, DR Ball, B Narasimham, A Anvar, ... IEEE Transactions on Nuclear Science 64 (1), 491-496, 2016 | 37 | 2016 |
| Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies H Zhang, H Jiang, TR Assis, DR Ball, K Ni, JS Kauppila, RD Schrimpf, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 5C-3-1-5C-3-5, 2016 | 35 | 2016 |
| Single-event upset characterization across temperature and supply voltage for a 20-nm bulk planar CMOS technology JS Kauppila, WH Kay, TD Haeffner, DL Rauch, TR Assis, NN Mahatme, ... IEEE Transactions on Nuclear Science 62 (6), 2613-2619, 2015 | 29 | 2015 |
| A TV digital interativa como ferramenta de apoio à educação infantil TA Tavares, CA Santos, TR Assis, CB Pinho, GM Carvalho, CS Costa Revista Brasileira de Informática na Educação 15 (2), 2007 | 27 | 2007 |
| Terrestrial SER characterization for nanoscale technologies: A comparative study NN Mahatme, B Bhuva, N Gaspard, T Assis, Y Xu, P Marcoux, M Vilchis, ... 2015 IEEE international reliability physics symposium, 4B. 4.1-4B. 4.7, 2015 | 17 | 2015 |
| Transistor sizing and folding techniques for radiation hardening FL Kastensmidt, T Assis, I Ribeiro, G Wirth, L Brusamarello, R Reis 2009 European Conference on Radiation and Its Effects on Components and …, 2009 | 15 | 2009 |
| Thermal neutron-induced soft-error rates for flip-flop designs in 16-nm bulk FinFET technology H Zhang, H Jiang, JD Brockman, TR Assis, X Fan, BL Bhuva, ... 2017 IEEE International Reliability Physics Symposium (IRPS), 3D-3.1-3D-3.4, 2017 | 12 | 2017 |
| Clustering Techniques and Statistical Fault Injection for Selective Mitigation of SEUs in Flip-Flops. A Evans, M Nicolaidis, SJ Wen, T Assis 14th International Symposium on Quality Electronic Design (ISQED) , 2013 …, 2013 | 12 | 2013 |
| SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process H Jiang, H Zhang, DR Ball, LW Massengill, BL Bhuva, TR Assis, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 3B-2-1-3B-2-6, 2016 | 11 | 2016 |
| Estimation of single-event transient pulse characteristics for predictive analysis TR Assis, JS Kauppila, BL Bhuva, RD Schrimpf, LW Massengill, R Wong, ... 2016 IEEE International Reliability Physics Symposium (IRPS), SE-5-1-SE-5-6, 2016 | 10 | 2016 |
| Kernel-based circuit partition approach to mitigate combinational logic soft errors NN Mahatme, NJ Gaspard, T Assis, I Chatterjee, TD Loveless, BL Bhuva, ... IEEE Transactions on Nuclear Science 61 (6), 3274-3281, 2014 | 9 | 2014 |
| High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process B Narasimham, K Chandrasekharan, JK Wang, G Djaja, NJ Gaspard, ... 2014 IEEE International Reliability Physics Symposium, 5F. 4.1-5F. 4.5, 2014 | 9 | 2014 |
| SER prediction in advanced finFET and SOI finFET technologies; challenges and comparisons to measurements K Lilja, M Bounasser, TR Assis, K Rodbell, P Oldiges, M Turowski, ... Single Event Effects (SEE) Symposium, 2016 | 8 | 2016 |
| Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies T Assis, FL Kastensmidt, G Wirth, R Reis 2009 10th Latin American Test Workshop, 1-6, 2009 | 8 | 2009 |
| Single-event performance of sense-amplifier based flip-flop design in a 16-nm bulk FinFET CMOS process H Jiang, H Zhang, TR Assis, B Narasimham, BL Bhuva, WT Holman, ... IEEE Transactions on Nuclear Science 64 (1), 477-482, 2016 | 6 | 2016 |
| Single-event upset responses of dual-and triple-well designs at advanced planar and FinFET technologies H Zhang, H Jiang, TR Assis, DR Ball, I Chatterjee, B Narasimham, ... 2016 16th European Conference on Radiation and Its Effects on Components and …, 2016 | 4 | 2016 |