| Characteristics of body-tied triple-gate pMOSFETs TS Park, HJ Cho, JD Choe, IH Cho, D Park, E Yoon, JH Lee IEEE electron device letters 25 (12), 798-800, 2004 | 29 | 2004 |
| Nano-scale SONOS memory with a double-gate MOSFET structure IH Cho, BG Park, JD Lee, JH Lee JOURNAL-KOREAN PHYSICAL SOCIETY 42, 233-236, 2003 | 19 | 2003 |
| Body-tied double-gate SONOS flash (omega flash) memory device built on bulk Si wafer IH Cho, TS Park, SY Choi, JD Lee, JH Lee 61st Device Research Conference. Conference Digest (Cat. No. 03TH8663), 133-134, 2003 | 13 | 2003 |
| Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure IH Cho, TS Park, JD Choe, HJ Cho, D Park, H Shin, BG Park, JD Lee, ... Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2006 | 12 | 2006 |
| Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate IHC Asif Ali, Dongsun Seo Journal of Semiconductor Technology and Science 17 (1), 156-161, 2017 | 10* | 2017 |
| Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor … DH Kim, S Park, Y Seo, TG Kim, DM Kim, IH Cho JSTS: Journal of Semiconductor Technology and Science 12 (4), 449-457, 2012 | 7 | 2012 |
| Analysis of the current path for a vertical NAND flash cell with program/erase states IHC Daewoong Kang, Hyoungsoo Kim, Asif Ali, Youngchang Yoon Semiconductor Science and Technology 31 (3), 035011(6p), 2016 | 5 | 2016 |
| Effects of Fabrication Process Variation on Impedance of Neural Probe Microelectrodes IJC Il Hwan Cho, Hyogeun Shin, Hyunjoo Jenny Lee Journal of Electrical Engineering & Technology 10 (3), 1138-1143, 2015 | 4 | 2015 |
| Reduction of ambipolar characteristics of vertical channel tunneling field-effect transistor by using dielectric sidewall CW Park, WY Choi, JH Lee, IH Cho Semiconductor science and technology 28 (11), 115002, 2013 | 4 | 2013 |
| Enhancement of Temperature Sensitivity for Metal–Insulator–Semiconductor Temperature Sensors by Using Bi2Mg2/3Nb4/3O7 Film JM Lee, IT Cho, JH Lee, SG Yoon, IH Cho Japanese Journal of Applied Physics 51 (8R), 080206, 2012 | 3 | 2012 |
| Modeling of sacrificial layer residue effect in nano-electro-mechanical nonvolatile memory YJ Jee, IH Cho Japanese Journal of Applied Physics 50 (10R), 100205, 2011 | 3 | 2011 |
| Highly scalable vertical channel phase change random access memory KS Kim, J Lee, IH Cho Japanese Journal of Applied Physics 50 (5R), 050206, 2011 | 3 | 2011 |
| Channel doping concentration and fin width effects on self-boosting in NAND-type SONOS flash memory array based on bulk-FinFETs S Cho, DH Li, DH Kim, IH Cho, BG Park 2009 IEEE Nanotechnology Materials and Devices Conference, 251-254, 2009 | 3 | 2009 |
| Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor N Xi, ES Cho, WY Choi, IH Cho Japanese Journal of Applied Physics 53 (11), 114201, 2014 | 2 | 2014 |
| Scaling down characteristics of vertical channel phase change random access memory (VPCRAM) CW Park, C Park, WY Choi, D Seo, C Jeong, IH Cho JSTS: Journal of Semiconductor Technology and Science 14 (1), 48-52, 2014 | 2 | 2014 |
| Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array KS Kim, IH Cho Japanese Journal of Applied Physics 51 (8R), 084302, 2012 | 1 | 2012 |
| Pull-In Voltage Modeling of Graphene Formed Nickel Nano Electro Mechanical Systems (NEMS) IHC Songnam Lim, Jong-Ho Lee, Woo Young Choi Journal of Semiconductor Technology and Science 15 (6), 647-652, 2015 | | 2015 |
| Thermal analysis of self-heating in saddle MOSFET devices HG Oh, C Jeong, IH Cho Japanese Journal of Applied Physics 53 (2), 020303, 2014 | | 2014 |
| Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application BK Park, WY Choi, ES Cho, IH Cho JSTS: Journal of Semiconductor Technology and Science 13 (4), 410-414, 2013 | | 2013 |
| Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors KH Park, IH Cho, JH Lee Japanese Journal of Applied Physics 48 (3R), 034501, 2009 | | 2009 |
