| FinFET-a self-aligned double-gate MOSFET scalable to 20 nm D Hisamoto, WC Lee, J Kedzierski, H Takeuchi, K Asano, C Kuo, ... IEEE transactions on electron devices 47 (12), 2320-2325, 2000 | 2399 | 2000 |
| Sub 50-nm finfet: Pmos X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 850 | 1999 |
| Sub-50 nm P-channel FinFET X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... IEEE Transactions on Electron Devices 48 (5), 880-886, 2001 | 621 | 2001 |
| A folded-channel MOSFET for deep-sub-tenth micron era D Hisamoto, WC Lee, J Kedzierski, E Anderson, H Takeuchi, K Asano, ... IEDM Tech. Dig 1998, 1032-1034, 1998 | 413 | 1998 |
| Observation of bulk defects by spectroscopic ellipsometry H Takeuchi, D Ha, TJ King Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 22 (4 …, 2004 | 289 | 2004 |
| Thermal budget limits of quarter-micrometer foundry CMOS for post-processing MEMS devices H Takeuchi, A Wung, X Sun, RT Howe, TJ King IEEE transactions on Electron Devices 52 (9), 2081-2086, 2005 | 177 | 2005 |
| Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric YC Yeo, Q Lu, P Ranade, H Takeuchi, KJ Yang, I Polishchuk, TJ King, ... IEEE Electron Device Letters 22 (5), 227-229, 2001 | 166 | 2001 |
| Work function engineering of molybdenum gate electrodes by nitrogen implantation P Ranade, H Takeuchi, TJ King, C Hu Electrochemical and Solid-State Letters 4 (11), G85, 2001 | 153 | 2001 |
| Vertical semiconductor devices including superlattice punch through stop layer and related methods R Mears, H Takeuchi, E Trautmann US Patent 9,275,996, 2016 | 111 | 2016 |
| Semiconductor devices including superlattice depletion layer stack and related methods R Mears, H Takeuchi, E Trautmann US Patent 9,406,753, 2016 | 103 | 2016 |
| Semiconductor device including a superlattice and replacement metal gate structure and related methods RJ Mears, TJK Liu, H Takeuchi US Patent 9,722,046, 2017 | 100 | 2017 |
| Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods RJ Mears, H Takeuchi US Patent 9,899,479, 2018 | 98 | 2018 |
| The radial bulk annular resonator: Towards a 50/spl Omega/RF MEMS filter B Bircumshaw, G Liu, H Takeuchi, TJ King, R Howe, O O'Reilly, A Pisano TRANSDUCERS'03. 12th International Conference on Solid-State Sensors …, 2003 | 96 | 2003 |
| Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods RJ Mears, H Takeuchi US Patent 9,941,359, 2018 | 88 | 2018 |
| Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap X Sun, Q Lu, V Moroz, H Takeuchi, G Gebara, J Wetzel, S Ikeda, C Shin, ... IEEE Electron Device Letters 29 (5), 491-493, 2008 | 82 | 2008 |
| Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory M She, H Takeuchi, TJ King IEEE Electron Device Letters 24 (5), 309-311, 2003 | 82 | 2003 |
| Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers RJ Mears, H Takeuchi, M Hytha US Patent 10,170,603, 2019 | 74 | 2019 |
| Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs D Ha, H Takeuchi, YK Choi, TJ King IEEE transactions on electron devices 51 (12), 1989-1996, 2004 | 70 | 2004 |
| Semiconductor device including resonant tunneling diode structure having a superlattice RJ Mears, H Takeuchi, M Hytha US Patent 10,453,945, 2019 | 68 | 2019 |
| Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice RJ Mears, H Takeuchi, M Hytha US Patent 10,249,745, 2019 | 67 | 2019 |
