| Transactionalizing legacy code: An experience report using GCC and memcached W Ruan, T Vyas, Y Liu, M Spear ACM SIGARCH Computer Architecture News 42 (1), 399-412, 2014 | 75 | 2014 |
| Stamp need not be considered harmful W Ruan, Y Liu, M Spear Ninth ACM SIGPLAN Workshop on Transactional Computing, 2014 | 57 | 2014 |
| Boosting timestamp-based transactional memory by exploiting hardware cycle counters W Ruan, Y Liu, M Spear ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-21, 2013 | 28 | 2013 |
| Transactional read-modify-write without aborts W Ruan, Y Liu, M Spear ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-24, 2015 | 17 | 2015 |
| Hybrid transactional memory revisited W Ruan, M Spear International Symposium on Distributed Computing, 215-231, 2015 | 12 | 2015 |
| Geometric work scheduling with dynamic and probabilistic work trimming T Kumar, W Jia, A Raman, H Chao, W Ruan US Patent 10,198,838, 2019 | 9 | 2019 |
| On the platform specificity of STM instrumentation mechanisms W Ruan, Y Liu, C Wang, M Spear Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation …, 2013 | 9 | 2013 |
| Fine-grained power optimization for heterogeneous parallel constructs W Ruan, H Zhao, T Kumar US Patent 10,296,074, 2019 | 5 | 2019 |
| Transactional Tools for the Third Decade M Kilgore, S Louie, C Wang, T Zhou, W Ruan, Y Liu, M Spear TRANSACT, 2015 | 5 | 2015 |
| Value prediction for security (VPsec): Countering fault attacks in modern microprocessors R Sheikh, R Cammarota, W Ruan 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 4 | 2018 |
| Symphony: Task scheduling and memory management in heterogeneous computing A Jindal, W Ruan Proceedings of the 5th International Workshop on OpenCL, 1-1, 2017 | 4 | 2017 |
| Geometric work scheduling with dynamic and probabilistic work trimming T Kumar, W Jia, A Raman, H Chao, W Ruan US Patent 10,325,390, 2019 | 2 | 2019 |
| Case study: Using transactions in memcached M Spear, W Ruan, Y Liu, T Vyas Transactional Memory. Foundations, Algorithms, Tools, and Applications: COST …, 2015 | 2 | 2015 |
| A blind digital watermarking algorithm based on chaotic systems X Hu, W Tian, Y Zheng, X Lian, W Ruan 2010 International Conference on Electrical and Control Engineering, 12-15, 2010 | 2 | 2010 |
| Methods for mitigating fault attacks in microprocessors using value prediction R Cammarota, RMA Al Sheikh, W Ruan US Patent App. 15/717,434, 2019 | 1 | 2019 |
| Geometric Work Scheduling of Irregularly Shaped Work Items H Chao, T Kumar, W Ruan, A Raman US Patent App. 15/358,515, 2018 | 1 | 2018 |
| Abstract Representation of Shared Data for Heterogeneous Computing T Kumar, A Natarajan, W Ruan, M Badr, D Suarez Gracia, C Cascaval The 30th International Workshop on Languages and Compilers for Parallel …, 2017 | 1 | 2017 |
| Accelerating Transactional Memory by Exploiting Platform Specificity W Ruan Lehigh University, 2015 | | 2015 |
| An Opaque Hybrid Transactional Memory W Ruan, M Spear TRANSACT, 2015 | | 2015 |
| On the Relationship Between Delaying Operators and Language-Level Semantics W Ruan, Y Liu, M Spear WTTM, 2013 | | 2013 |
