Hans-Joachim Wunderlich

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Sybille HellebrandUniversity of Paderborn, GermanyVerified email at uni-paderborn.de
Michael A. KochteNumascale AS, prev. Univ. Stuttgart GermanyVerified email at iti.uni-stuttgart.de
Bernd BeckerProfessor of Computer Science, University of FreiburgVerified email at informatik.uni-freiburg.de
Stefan HolstKyushu Institute of TechnologyVerified email at ci.kyutech.ac.jp
Patrick GirardLIRMMVerified email at lirmm.fr
Eric SchneiderUniversity of Stuttgart, Institute of Computer Architecture and Computer EngineeringVerified email at iti.uni-stuttgart.de
Rafal BaranowskiRobert Bosch GmbHVerified email at iti.uni-stuttgart.de
Xiaoqing WenKyushu Institute of TechnologyVerified email at cse.kyutech.ac.jp
Jörg HenkelProfessor of Computer Science, Karlsruhe Institute of TechnologyVerified email at kit.edu
Lars BauerResearch Group Leader, Computer Science, Karlsruhe Institute of Technology (KIT)Verified email at kit.edu
Arnaud VirazelLIRMM - Univ. Montpellier / CNRSVerified email at lirmm.fr
Jürgen TeichFull Professor, Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergVerified email at cs.fau.de
Mehdi B. TahooriProfessor of Computer Science, Karlsruhe Institute of Technology, GermanyVerified email at kit.edu
Michael GlaßProfessor at Ulm UniversityVerified email at uni-ulm.de
Norbert WehnUniversity of KaiserslauternVerified email at eit.uni-kl.de
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringVerified email at polito.it
Nur ToubaProfessor of Electrical and Computer Engineering, University of Texas at AustinVerified email at ece.utexas.edu

Hans-Joachim Wunderlich

Professor Emeritus of Computer Science, University of Stuttgart

Verified email at informatik.uni-stuttgart.de - Homepage

Computer Engineering Computer Architecture Dependability Test Fault Tolerance


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Minimized Power Consumption for Scan-Based BIST S Gerstendörfer, HJ Wunderlich IEEE International Test Conference (ITC'99) 30, 77-84, 1999	515	1999
Bit-flipping BIST HJ Wunderlich, G Kiefer Proceedings of International Conference on Computer Aided Design, 337-343, 1996	316	1996
Multiple distributions for biased random test patterns HJ Wunderlich IEEE transactions on computer-aided design of integrated circuits and …, 1990	306	1990
Power-aware design-for-test HJ Wunderlich, CG Zoellin Power-Aware Testing and Test Strategies for Low Power Devices, 117-146, 2009	303*	2009
A modified clock scheme for a low power BIST test pattern generator P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001	217	2001
Pattern generation for a deterministic BIST scheme S Hellebrand, B Reeb, S Tarnick, HJ Wunderlich Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995	202	1995
A mixed mode BIST scheme based on reseeding of folding counters S Hellebrand, HG Liang, HJ Wunderlich Journal of Electronic Testing 17, 341-349, 2001	198	2001
Low power serial built-in self-test A Hertwig, HJ Wunderlich Proceedings of IEEE European Test Workshop, 1998, 1998	177	1998
Two-dimensional test data compression for scan-based deterministic BIST HG Liang, S Hellebrand, HJ Wunderlich Journal of Electronic Testing 18, 159-170, 2002	160	2002
Adaptive Debug and Diagnosis Without Fault Dictionaries S Holst, HJ Wunderlich IEEE European Test Symposium (ETS'07) 12, 7-12, 2007	146	2007
PROTEST: A tool for probabilistic testability analysis HJ Wunderlich 22nd ACM/IEEE Design Automation Conference, 204-211, 1985	144	1985
An analytical approach to the partial scan problem A Kunzmann, HJ Wunderlich Journal of Electronic Testing 1, 163-174, 1990	141	1990
X-Masking During Logic BIST and its Impact on Defect Coverage Y Tang, HJ Wunderlich, P Engelke, I Polian, B Becker, J Schlöffel, ... IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14 (2), 193-202, 2006	134	2006
Self test using unequiprobable random patterns HJ Wunderlich Verlag nicht ermittelbar, 1987	132	1987
Application of deterministic logic BIST on industrial circuits G Kiefer, H Vranken, E Jan Marinissen, HJ Wunderlich Journal of Electronic Testing 17, 351-362, 2001	129	2001
Design and architectures for dependable embedded systems J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ... Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011	122	2011
An integrated built-in test and repair approach for memories with 2D redundancy P Ohler, S Hellebrand, HJ Wunderlich 12th IEEE European Test Symposium (ETS'07), 91-96, 2007	122	2007
Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen B Bertsche, P Göhner, U Jensen, W Schinköthe, HJ Wunderlich Springer-Verlag, 2009	117	2009
Accumulator based deterministic BIST R Dorsch, HJ Wunderlich Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998	110	1998
Mixed-Mode BIST Using Embedded Processors S Hellebrand, HJ Wunderlich, A Hertwig IEEE International Test Conference (ITC'96) 27, 195-204, 1996	109	1996

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