| MATIC: Learning around errors for efficient low-voltage neural network accelerators S Kim, P Howe, T Moreau, A Alaghi, L Ceze, V Sathe 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2018 | 87 | 2018 |
| Energy-efficient neural network acceleration in the presence of bit-level memory errors S Kim, P Howe, T Moreau, A Alaghi, L Ceze, VS Sathe IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4285-4298, 2018 | 57 | 2018 |
| QAPPA: A framework for navigating quality-energy tradeoffs with arbitrary quantization T Moreau, F Augusto, P Howe, A Alaghi, L Ceze Technical Report UW-CSE-17-03-02, 2017 | 11 | 2017 |
| MIMIC: Masked Image Modeling with Image Correspondences K Marathe, M Bigverdi, N Khan, T Kundu, P Howe, A Bhattad, A Kembhavi, ... Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2024 | 1 | 2024 |
| Special session paper: exploiting quality-energy tradeoffs with arbitrary quantization T Moreau, F Augusto, P Howe, A Alaghi, L Ceze 2017 International Conference on Hardware/Software Codesign and System …, 2017 | | 2017 |
| MATIC: Adaptation and In-Situ Canaries for Energy-Efficient Neural Network Acceleration S Kim, P Howe, T Moreau, A Alaghi, L Ceze, V Sathe | | |
