| Charge collection and charge sharing in a 130 nm CMOS technology OA Amusan, AF Witulski, LW Massengill, BL Bhuva, PR Fleming, ML Alles, ... IEEE Transactions on nuclear science 53 (6), 3253-3258, 2006 | 491 | 2006 |
| Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies B Narasimham, BL Bhuva, RD Schrimpf, LW Massengill, MJ Gadlage, ... IEEE Transactions on Nuclear Science 54 (6), 2506-2511, 2007 | 231 | 2007 |
| Single-event transient pulse quenching in advanced CMOS logic circuits JR Ahlbin, LW Massengill, BL Bhuva, B Narasimham, MJ Gadlage, ... IEEE Transactions on Nuclear Science 56 (6), 3050-3056, 2009 | 199 | 2009 |
| Comparison of combinational and sequential error rates for a deep submicron process NN Mahatme, S Jagannathan, TD Loveless, LW Massengill, BL Bhuva, ... IEEE Transactions on Nuclear Science 58 (6), 2719-2725, 2011 | 188 | 2011 |
| RHBD techniques for mitigating effects of single-event hits using guard-gates A Balasubramanian, BL Bhuva, JD Black, LW Massengill IEEE Transactions on Nuclear Science 52 (6), 2531-2535, 2005 | 177 | 2005 |
| Neutron-and proton-induced single event upsets for D-and DICE-flip/flop designs at a 40 nm technology node TD Loveless, S Jagannathan, T Reece, J Chetia, BL Bhuva, MW McCurdy, ... IEEE Transactions on Nuclear Science 58 (3), 1008-1014, 2011 | 176 | 2011 |
| On-chip characterization of single-event transient pulsewidths B Narasimham, V Ramachandran, BL Bhuva, RD Schrimpf, AF Witulski, ... IEEE Transactions on Device and Materials Reliability 6 (4), 542-549, 2006 | 173 | 2006 |
| Single event upsets in deep-submicrometer technologies due to charge sharing OA Amusan, LW Massengill, MP Baze, AL Sternberg, AF Witulski, ... IEEE Transactions on Device and Materials Reliability 8 (3), 582-589, 2008 | 147 | 2008 |
| A hardened-by-design technique for RF digital phase-locked loops TD Loveless, LW Massengill, BL Bhuva, WT Holman, AF Witulski, ... IEEE transactions on nuclear science 53 (6), 3432-3438, 2006 | 143 | 2006 |
| A single-event-hardened phase-locked loop fabricated in 130 nm CMOS TD Loveless, LW Massengill, BL Bhuva, WT Holman, RA Reed, ... IEEE transactions on nuclear science 54 (6), 2012-2020, 2007 | 136 | 2007 |
| Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor LW Massengill, AE Baranski, DO Van Nort, J Meng, BL Bhuva IEEE Transactions on Nuclear Science 47 (6), 2609-2615, 2000 | 135 | 2000 |
| HBD layout isolation techniques for multiple node charge collection mitigation JD Black, AL Sternberg, ML Alles, AF Witulski, BL Bhuva, LW Massengill, ... IEEE transactions on nuclear science 52 (6), 2536-2541, 2005 | 134 | 2005 |
| Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS S DasGupta, AF Witulski, BL Bhuva, ML Alles, RA Reed, OA Amusan, ... IEEE Transactions on Nuclear Science 54 (6), 2407-2412, 2007 | 133 | 2007 |
| Layout technique for single-event transient mitigation via pulse quenching NM Atkinson, AF Witulski, WT Holman, JR Ahlbin, BL Bhuva, ... IEEE Transactions on Nuclear Science 58 (3), 885-890, 2011 | 126 | 2011 |
| Design techniques to reduce SET pulse widths in deep-submicron combinational logic OA Amusan, LW Massengill, BL Bhuva, S DasGupta, AF Witulski, ... IEEE Transactions on Nuclear Science 54 (6), 2060-2064, 2007 | 125 | 2007 |
| The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process JR Ahlbin, MJ Gadlage, DR Ball, AW Witulski, BL Bhuva, RA Reed, ... IEEE Transactions on Nuclear Science 57 (6), 3380-3385, 2010 | 123 | 2010 |
| Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology BD Olson, OA Amusan, S Dasgupta, LW Massengill, AF Witulski, ... IEEE Transactions on Nuclear Science 54 (4), 894-897, 2007 | 123 | 2007 |
| Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes MJ Gadlage, JR Ahlbin, B Narasimham, BL Bhuva, LW Massengill, ... IEEE Transactions on Nuclear Science 57 (6), 3336-3341, 2010 | 121 | 2010 |
| Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process OA Amusan, LW Massengill, MP Baze, BL Bhuva, AF Witulski, JD Black, ... IEEE Transactions on device and Materials Reliability 9 (2), 311-317, 2009 | 120 | 2009 |
| Modeling and mitigating single-event transients in voltage-controlled oscillators TD Loveless, LW Massengill, WT Holman, BL Bhuva IEEE Transactions on Nuclear Science 54 (6), 2561-2567, 2007 | 117 | 2007 |
Lloyd MassengillVanderbilt UniversityVerified email at vanderbilt.edu
