| Relative timing [asynchronous design] KS Stevens, R Ginosar, S Rotem IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (1), 129-140, 2003 | 234 | 2003 |
| An asynchronous instruction length decoder KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ... IEEE Journal of solid-state circuits 36 (2), 217-228, 2001 | 116 | 2001 |
| RAPPID: An asynchronous instruction length decoder S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ... Proceedings. Fifth International Symposium on Advanced Research in …, 1999 | 116 | 1999 |
| The Post Office experience: Designing a large asynchronous chip A Davis, B Coates, K Stevens [1993] Proceedings of the Twenty-sixth Hawaii International Conference on …, 1993 | 94 | 1993 |
| The Post Office experience: Designing a large asynchronous chip B Coates, AL Davis, K Stevens Integration 15 (3), 341-366, 1993 | 85 | 1993 |
| Practical verification and synthesis of low latency asynchronous systems. KS Stevens University of Calgary, 1995 | 72 | 1995 |
| The Post Office-Communication Support for Distributed Ensemble Architectures. KS Stevens, SV Robison, AL Davis ICDCS, 160-166, 1986 | 67 | 1986 |
| Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate MC Morrise, KS Stevens US Patent 6,557,149, 2003 | 66 | 2003 |
| Characterization of asynchronous templates for integration into clocked CAD flows KS Stevens, Y Xu, V Vij 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 151-161, 2009 | 63 | 2009 |
| Apparatus for multi-processor communications AL Davis, SV Robison, KS Stevens US Patent 4,922,408, 1990 | 59 | 1990 |
| Automatic Synthesis of Fast Compact Asynchronous Control Circuits. A Davis, B Coates, K Stevens Asynchronous Design Methodologies 28, 193-207, 1993 | 58 | 1993 |
| Efficient statistical capacitance variability modeling with orthogonal principle factor analysis R Jiang, W Fu, JM Wang, V Lin, CCP Chen ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 54* | 2005 |
| Relative timing based verification of timed circuits and systems H Kim, PA Beerel, K Stevens Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002 | 49 | 2002 |
| Energy and performance models for synchronous and asynchronous communication KS Stevens, P Golani, PA Beerel IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (3), 369-382, 2010 | 39 | 2010 |
| Energy and performance models for clocked and asynchronous communication KS Stevens Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003 | 39 | 2003 |
| Clock gating with an asynchronous wrapper cell KS Stevens, D Bhadra US Patent 9,753,486, 2017 | 38 | 2017 |
| Method and system for asynchronous chip design KS Stevens US Patent 8,065,647, 2011 | 38 | 2011 |
| Design of an energy-efficient asynchronous NoC and its optimization tools for heterogeneous SoCs D Gebhardt, J You, KS Stevens IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 36 | 2011 |
| Branch instruction handling in a self-timed marking system R Ginosar, R Kol, KS Stevens, PA Beerel, KY Yun, CJ Myers, S Rotem US Patent 5,931,944, 1999 | 36 | 1999 |
| Automatic synthesis of computation interference constraints for relative timing verification Y Xu, KS Stevens 2009 IEEE International Conference on Computer Design, 16-22, 2009 | 35 | 2009 |
Ran GinosarProfessor of EE & CS, TechnionVerified email at ee.technion.ac.il
