| Method and apparatus for using compression to improve performance of low voltage caches J Kalamatianos, S Ganapathy, S Das, M Tomei US Patent 10,884,940, 2021 | 28 | 2021 |
| COMPRESSION METADATA ASSISTED COMPUTATION M Tomei, S Das US Patent App. 17/033,308, 2022 | 26 | 2022 |
| The future of formal methods and GALS design KS Stevens, D Gebhardt, J You, Y Xu, V Vij, S Das, K Desai Electronic Notes in Theoretical Computer Science 245, 115-134, 2009 | 25 | 2009 |
| DYNAMIC PRECISION SCALING AT EPOCH GRANULARITY IN NEURAL NETWORKS SN Das, A Vishnu US Patent App. 16/425,403, 2020 | 16 | 2020 |
| SAS: Source asynchronous signaling protocol for asynchronous handshake communication free from wire delay overhead S Das, V Vij, KS Stevens Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International …, 2013 | 11 | 2013 |
| Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study E Kilada, S Das, K Stevens VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP, 7-12, 2010 | 11 | 2010 |
| Predict; Do not React for Enabling Efficient Fine Grain DVFS in GPUs S Bharadwaj, S Das, K Mazumdar, B Beckmann, S Kosonocky arXiv preprint arXiv:2205.00121, 2022 | 10 | 2022 |
| DUB: dynamic underclocking and bypassing in nocs for heterogeneous GPU workloads S Bharadwaj, S Das, Y Eckert, M Oskin, T Krishna Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip …, 2021 | 9 | 2021 |
| Controlling the operating speed of stages of an asynchronous pipeline G Sadowski, J Kalamatianos, SN Das US Patent 10,698,692, 2020 | 7 | 2020 |
| System and method for energy reduction based on history of reliability of a system G Sadowski, SE Raasch, SN Das, W Burleson US Patent 10,318,363, 2019 | 7* | 2019 |
| Byte select cache compression SN Das, M Tomei, DA Wood US Patent 10,860,489, 2020 | 5 | 2020 |
| Hint-based fine-grained dynamic voltage and frequency scaling in gpus SN Das, JL Greathouse US Patent App. 16/213,126, 2020 | 5 | 2020 |
| Compressing data for storage in cache memories in a hierarchy of cache memories MJ Tomei, PB Bedoukian, SN Das US Patent 10,795,825, 2020 | 4 | 2020 |
| A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols MJ Wibbels, S Das, DS Takur, V Nori, KS Stevens 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems …, 2019 | 4 | 2019 |
| Data compression system using base values and methods thereof S Seyedzadehdelcheh, X Zhang, B Beckmann, SN Das US Patent 11,144,208, 2021 | 3 | 2021 |
| Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm S Das, G Manetas, KS Stevens, R Suaya Networks on Chip (NoCS), 2013 Seventh IEEE/ACM International Symposium on, 1-2, 2013 | 3 | 2013 |
| Apparatus and method for providing workload distribution of threads among multiple compute units K Rao, SN Das, X An, W Huang US Patent 11,194,634, 2021 | 2 | 2021 |
| Resource-aware compression S Seyedzadehdelcheh, SN Das, BM Beckmann US Patent App. 16/725,971, 2021 | 2 | 2021 |
| Device and method for cache utilization aware data compression SN Das, K Punniyamurthy, M Tomei, BM Beckmann US Patent 10,838,727, 2020 | 2 | 2020 |
| Pattern-based cache block compression M Tomei, SN Das, DA Wood US Patent App. 17/029,158, 2021 | 1 | 2021 |
Ken StevensProfessor of electrical and computer engineering, university of utahVerified email at ece.utah.edu