| Temperature and size effect on the electrical properties of monolayer graphene based interconnects for next generation MQCA based nanoelectronics S Debroy, S Sivasubramani, G Vaidya, SG Acharyya, A Acharyya Scientific Reports 10 (1), 6240, 2020 | 37 | 2020 |
| Tunable intrinsic magnetic phase transition in pristine single-layer graphene nanoribbons S Sivasubramani, S Debroy, S Acharyya, A Acharyya Nanotechnology, 2018 | 20 | 2018 |
| Shape and Positional Anisotropy Based Area Efficient Magnetic Quantum-Dot Cellular Automata Design Methodology for Full Adder Implementation S Sivasubramani, V Mattela, C Pal, MS Islam, A Acharyya IEEE Transactions on Nanotechnology 17 (6), 1303-1307, 2018 | 19 | 2018 |
| Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder design approach S Sivasubramani, V Mattela, C Pal, A Acharyya Nanotechnology 31 (2), 025202, 2019 | 18 | 2019 |
| Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate S Sivasubramani, V Mattela, C Pal, A Acharyya Nanotechnology 30 (37), 37LT02, 2019 | 15 | 2019 |
| Nanomagnetic logic based runtime Reconfigurable area efficient and high speed adder design methodology S Sivasubramani, V Mattela, P Rangesh, C Pal, A Acharyya Nanotechnology 31 (18), 18LT02, 2020 | 11 | 2020 |
| Design and development of a security module with inbuilt neural network methodologies and an advanced technique on fingerprint recognition S Santhosh 2014 International Conference on Circuits, Power and Computing Technologies …, 2014 | 8 | 2014 |
| Investigation on electronic transport and magnetic properties of graphene for its applications in nanomagnetic computing S Sivasubramani Indian Institute of Technology Hyderabad, 2018 | 7 | 2018 |
| ANFIS based HVDC control and fault identification of HVDC converter S Santhosh 2012 International Conference on Emerging Trends in Electrical Engineering …, 2012 | 5 | 2012 |
| Area efficient in-plane nanomagnetic multiplier and convolution architecture design S Sivasubramani, S Debroy, A Acharyya Nano Express 2 (2), 020008, 2021 | 4 | 2021 |
| Innovative methodology and designing of intelligent mobile robots computer vision with genetic algorithm SLE mechanism and advanced sensors in managing disaster S Santhosh 2014 International Conference on Circuits, Power and Computing Technologies …, 2014 | 4 | 2014 |
| Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate S Sivasubramani, B Paikaray, M Kuchibhotla, A Haldar, C Murapaka, ... Nanotechnology 34 (13), 13LT01, 2023 | 3 | 2023 |
| A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design V Mattela, S Debroy, S Sivasubramani, A Acharyya Nanotechnology 32 (9), 095205, 2020 | 3 | 2020 |
| Nanoscale VLSI: Devices, Circuits and Applications R Dhiman, R Chandel Springer Nature, 2020 | 3 | 2020 |
| Rebooting Computing: Nanomagnetic Logic Based Computing Architecture Design Methodology S Sivasubramani Indian Institute of Technology Hyderabad, 2020 | 3 | 2020 |
| Nanomagnetic computing for next generation interconnects and logic design S Debroy, S Sivasubramani, SG Acharyya, A Acharyya | 3 | 2019 |
| Soft-I-Robot using neural networks and genetic algorithm S Santhosh Indian Journal of Innovations and Developments 1 (6), 441-449, 2012 | 3 | 2012 |
| The first edition of the World Nanotechnology Marathon [Spotlight Column] MB Lodi, S Sivasubramani, J Berkenbrock, D Vieira, T Welsch, Y Li, R Sliz IEEE Nanotechnology Magazine 16 (5), 9-12, 2022 | 2 | 2022 |
| Interlayer Exchange Coupled Based Nanomagnetic Multiplier Architecture Design Methodology V Mattela, S Debroy, S Sivasubramani, A Acharyya IEEE Transactions on Nanotechnology 20, 744-753, 2021 | 2 | 2021 |
| Graphene-based area efficient power planning architecture design methodology for nanomagnetic logic implementation S Sivasubramani, S Debroy, S Ghosh Acharyya, A Acharyya The Journal of Supercomputing 79 (18), 20961-20983, 2023 | 1 | 2023 |
Amit AcharyyaProfessor, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, IndiaVerified email at iith.ac.in