| Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs H Thapliyal, N Ranganathan ACM Journal on Emerging Technologies in Computing Systems (JETC) 6 (4), 14, 2010 | 280 | 2010 |
| A survey of affective computing for stress detection: Evaluating technologies in stress detection for better health S Greene, H Thapliyal, A Caban-Holt IEEE Consumer Electronics Magazine 5 (4), 44-56, 2016 | 223 | 2016 |
| Reversible logic-based concurrently testable latches for molecular QCA H Thapliyal, N Ranganathan IEEE transactions on nanotechnology 9 (1), 62-69, 2009 | 216 | 2009 |
| Design of efficient reversible binary subtractors based on a new reversible gate H Thapliyal, N Ranganathan 2009 IEEE computer society Annual symposium on VLSI, 229-234, 2009 | 205 | 2009 |
| Design of Testable Reversible Sequential Circuits H Thapliyal, N Ranganathan, S Kotiyal IEEE Transactions on VLSI 21 (7), 1201-1209, 2013 | 200 | 2013 |
| A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures H Thapliyal, MB Srinivas Asia-Pacific Conference on Advances in Computer Systems Architecture, 805-817, 2005 | 184 | 2005 |
| Novel reversible multiplier architecture using reversible TSG gate H Thapliyal, MB Srinivas arXiv preprint cs/0605004, 2006 | 177 | 2006 |
| A beginning in the reversible logic synthesis of sequential circuits H Thapliyal, MB Srinivas, M Zwolinski | 164 | 2005 |
| Design of efficient reversible logic based binary and bcd adder circuits H Thapliyal, N Ranganathan ACM Journal of Emerging Technologies in Computing Systems 9 (3), 17:1--17:31, 2013 | 146 | 2013 |
| Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing C Labrado, H Thapliyal Electronics Letters 52 (6), 464-466, 2016 | 139 | 2016 |
| Design of reversible sequential elements with feasibility of transistor implementation H Thapliyal, AP Vinod 2007 IEEE International Symposium on Circuits and Systems, 625-628, 2007 | 134 | 2007 |
| High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics H Thapliyal, MB Srinivas Enformatika Trans 2, 225-228, 2004 | 124 | 2004 |
| A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. H Thapliyal, HR Arabnia ESA/VLSI, 434-439, 2004 | 114 | 2004 |
| Quantum Circuit Design of A T-count Optimized Integer Multiplier E Munoz-Coreas, H Thapliyal IEEE Transactions on Computers 68 (5), 729-739, 2019 | 111* | 2019 |
| Design of reversible latches optimized for quantum cost, delay and garbage outputs H Thapliyal, N Ranganathan 2010 23rd International Conference on VLSI Design, 235-240, 2010 | 111 | 2010 |
| Stress Detection and Management: A Survey of Wearable Smart Health Devices H Thapliyal, V Khalus, C Labrado IEEE Consumer Electronics Magazine 6 (4), 64-69, 2017 | 106 | 2017 |
| Mach-Zehnder interferometer based design of all optical reversible binary adder S Kotiyal, H Thapliyal, N Ranganathan 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 721-726, 2012 | 101 | 2012 |
| Design of a comparator tree based on reversible logic H Thapliyal, N Ranganathan, R Ferreira 10th IEEE International Conference on Nanotechnology, 1113-1116, 2010 | 98 | 2010 |
| Novel BCD adders and their reversible logic implementation for IEEE 754r format H Thapliyal, S Kotiyal, MB Srinivas 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 98 | 2006 |
| A new design of the reversible subtractor circuit H Thapliyal, N Ranganathan 2011 11th IEEE International Conference on Nanotechnology, 1430-1435, 2011 | 97 | 2011 |
Dinesh Kumar SelvakumaranGPU Design and Electrical Analysis Engineer, Apple Inc.Verified email at apple.com
