| 2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET S Roy, A Chatterjee, DK Sinha, R Pirogova, S Baishya IEEE Transactions on Electron Devices 64 (5), 2106-2112, 2017 | 13 | 2017 |
| Modeling Erratic Behavior Due to High Current Filamentation in Bipolar Structures Under Dynamic Avalanche Conditions DK Sinha, A Chatterjee, RD Schrimpf IEEE Transactions on Electron Devices 63 (8), 3185-3192, 2016 | 6 | 2016 |
| Fast ionization-front-induced anomalous switching behavior in trigger bipolar transistors of Marx-bank circuits under base-drive conditions DK Sinha, MS Ansari, A Ray, G Trivedi, A Chatterjee, RD Schrimpf IEEE Transactions on Plasma Science 46 (6), 2064-2071, 2018 | 2 | 2018 |
| A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach V Abhinav, DK Sinha, A Chatterjee, F Brewer 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 2 | 2016 |
| Design of band-gap engineered silicon-germanium Junctionless Double-gate FET for ZRAM application DK Sinha, A Chatterjee, G Trivedi, V Koldyaev 2015 6th International Conference on Computers and Devices for Communication …, 2015 | 2 | 2015 |
| Methodology for optimizing ESD protection for high speed LVDS based I/Os V Abhinav, A Chatterjee, DK Sinha, R Singh 2015 19th International Symposium on VLSI Design and Test, 1-5, 2015 | 2 | 2015 |
| SPICE level implementation of physics of filamentation in ESD protection devices DK Sinha, A Chatterjee Microelectronics Reliability 79, 239-247, 2017 | 1 | 2017 |
| FEM Based Device Simulator for High Voltage Devices A Ray, G Kumar, S Bordoloi, DK Sinha, P Agarwal, G Trivedi VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | 1 | 2017 |
| FEM Based Device Simulator for High Voltage Devices DK Sinha, P Agarwal, G Trivedi VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | | 2017 |
| Modeling ambipolar behavior under high current injection regimes in layered semiconductor device structures DK Sinha Guwahati, 2017 | | 2017 |
| Two Dimensional Numerical Simulator for Modeling NDC Region in SNDC Devices DK Sinha, A Chatterjee, G Trivedi Journal of Physics: Conference Series 759 (1), 012099, 2016 | | 2016 |
| A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET DK Sinha, A Chatterjee, V Abhinav, G Trivedi, V Koldyaev 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | | 2016 |
Ron SchrimpfProfessor of Electrical Engineering, Vanderbilt UniversityVerified email at vanderbilt.edu