| A performance analysis framework for optimizing OpenCL applications on FPGAs Z Wang, B He, W Zhang, S Jiang 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 119 | 2016 |
| Pymtl3: A python framework for open-source hardware modeling, generation, simulation, and verification S Jiang, P Pan, Y Ou, C Batten IEEE Micro 40 (4), 58-66, 2020 | 62 | 2020 |
| Mamba: closing the performance gap in productive hardware development frameworks S Jiang, B Ilbeyi, C Batten Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 39 | 2018 |
| PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks C Tan, Y Ou, S Jiang, P Pan, C Torng, S Agwa, C Batten 37th IEEE International Conference on Computer Design (ICCD), 2019 | 20 | 2019 |
| Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs J Kim, S Jiang, C Torng, M Wang, S Srinath, B Ilbeyi, K Al-Hawaj, C Batten Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 15 | 2017 |
| An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework S Jiang, C Torng, C Batten First Workshop on Open-Source EDA Technology (WOSET 2018), 2018 | 14 | 2018 |
| Bank stealing for conflict mitigation in GPGPU register file N Jing, S Chen, S Jiang, L Jiang, C Li, X Liang 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 14 | 2015 |
| PyH2: Using PyMTL3 to create productive and open-source hardware testing methodologies S Jiang, Y Ou, P Pan, K Cheng, Y Zhang, C Batten IEEE Design & Test 38 (2), 53-61, 2020 | 9 | 2020 |
| Bank stealing for a compact and efficient register file architecture in GPGPU N Jing, S Jiang, S Chen, J Zhang, L Jiang, C Li, X Liang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 520-533, 2016 | 7 | 2016 |
| A study of sorting algorithms on approximate memory S Chen, S Jiang, B He, X Tang 2016 International Conference on Management of Data (SIGMOD), 647-662, 2016 | 7 | 2016 |
| A New Era of Silicon Prototyping in Computer Architecture Research C Torng, S Jiang, K Al-Hawaj, I Bukreyev, B Ilbeyi, T Ta, L Cheng, ... The RISC-V Day Workshop at the 51st Int’l Symp. on Microarchitecture, 2018 | 4 | 2018 |
| UMOC: Unified Modular Ordering Constraints to Unify Cycle-and Register-Transfer-Level Modeling S Jiang, Y Ou, P Pan, C Batten 2021 58th ACM/IEEE Design Automation Conference (DAC), 883-888, 2021 | 2 | 2021 |
| Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages P Pan, S Jiang, Y Ou, C Batten Proceedings of the 21st ACM-IEEE International Conference on Formal Methods …, 2023 | 1 | 2023 |
| Towards Gradually Typed Hardware Description Languages P Pan, S Jiang, Y Ou, C Batten Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE …, 2023 | 1 | 2023 |
| Guest Editors' Introduction: The Resurgence of Open-Source EDA Technology S Jiang, Y Ou, P Pan, K Cheng, Y Zhang, C Batten IEEE DESIGN & TEST 38 (2), 53-61, 2021 | | 2021 |
| Productive and Extensible Hardware Modeling, Simulation, and Verification Methodologies S Jiang Cornell University, 2021 | | 2021 |
Christopher BattenCornell UniversityVerified email at cornell.edu