| Interconnect limits on gigascale integration (GSI) in the 21st century JA Davis, R Venkatesan, A Kaloyeros, M Beylansky, SJ Souri, K Banerjee, ... Proceedings of the IEEE 89 (3), 305-324, 2001 | 960 | 2001 |
| Limits on silicon nanoelectronics for terascale integration JD Meindl, Q Chen, JA Davis Science 293 (5537), 2044-2049, 2001 | 540 | 2001 |
| A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation JA Davis, VK De, JD Meindl IEEE Transactions on Electron Devices 45 (3), 580-589, 1998 | 510* | 1998 |
| Interconnect opportunities for gigascale integration JD Meindl, JA Davis, P Zarkesh-Ha, CS Patel, KP Martin, PA Kohl IBM journal of research and development 46 (2.3), 245-263, 2002 | 240 | 2002 |
| Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions JA Davis, JD Meindl IEEE Transactions on Electron Devices 47 (11), 2068-2077, 2000 | 215 | 2000 |
| The fundamental limit on binary switching energy for terascale integration (TSI) JD Meindl, JA Davis IEEE Journal of Solid-State Circuits 35 (10), 1515-1516, 2000 | 209 | 2000 |
| Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks JA Davis, JD Meindl IEEE Transactions on Electron Devices 47 (11), 2078-2087, 2000 | 181 | 2000 |
| Compact distributed RLC interconnect models-part IV: unified models for time delay, crosstalk, and repeater insertion R Venkatesan, JA Davis, JD Meindl IEEE Transactions on Electron Devices 50 (4), 1094-1102, 2003 | 125 | 2003 |
| Impact of three-dimensional architectures on interconnects in gigascale integration JW Joyner, R Venkatesan, P Zarkesh-Ha, JA Davis, JD Meindl IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (6), 922-928, 2001 | 109 | 2001 |
| Interconnect technology and design for gigascale integration JA Davis, JD Meindl Springer Science & Business Media, 2012 | 100 | 2012 |
| Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) R Venkatesan, JA Davis, KA Bowman, JD Meindl IEEE transactions on very large scale integration (VLSI) systems 9 (6), 899-912, 2001 | 85 | 2001 |
| Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip P Zarkesh-Ha, JA Davis, JD Meindl IEEE transactions on very large scale integration (VLSI) systems 8 (6), 649-659, 2000 | 84 | 2000 |
| Compact distributed RLC interconnect models-Part III: Transients in single and coupled lines with capacitive load termination R Venkatesan, JA Davis, JD Meindl IEEE transactions on Electron Devices 50 (4), 1081-1093, 2003 | 73 | 2003 |
| A three-dimensional stochastic wire-length distribution for variable separation of strata JW Joyner, P Zarkesh-Ha, JA Davis, JD Meindl Proceedings of the IEEE 2000 International Interconnect Technology …, 2000 | 71 | 2000 |
| Interconnecting device opportunities for gigascale integration (GSI) JD Meindl, R Venkatesan, JA Davis, J Joyner, A Naeemi, P Zarkesh-Ha, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 58 | 2001 |
| Optimization of throughput performance for low-power VLSI interconnects VV Deodhar, JA Davis IEEE transactions on very large scale integration (VLSI) systems 13 (3), 308-318, 2005 | 54 | 2005 |
| Prediction of interconnect fan-out distribution using Rent's rule P Zarkesh-Ha, JA Davis, W Loh, JD Meindl Proceedings of the 2000 international workshop on System-level interconnect …, 2000 | 51 | 2000 |
| IEEE Trans. Electron Devices JA Davis, A Rohatgi, RH Hopkins, P Blais, P Rai-Choudhury, ... IEEE Trans. Electron Devices 45 (3), 580-589, 1998 | 49 | 1998 |
| IntSim: A CAD tool for optimization of multilevel interconnect networks DC Sekar, A Naeemi, R Sarvari, JA Davis, JD Meindl 2007 IEEE/ACM International Conference on Computer-Aided Design, 560-567, 2007 | 48 | 2007 |
| A compact physical via blockage model Q Chen, JA Davis, P Zarkesh-Ha, JD Meindl IEEE transactions on very large scale integration (VLSI) systems 8 (6), 689-692, 2000 | 46 | 2000 |
Keith BowmanQualcomm; Intel; Georgia Institute of TechnologyVerified email at qti.qualcomm.com
