| RideNN: A new rider optimization algorithm-based neural network for fault diagnosis in analog circuits D Binu, BS Kariyappa IEEE Transactions on Instrumentation and Measurement 68 (1), 2-26, 2018 | 340 | 2018 |
| A survey on fault diagnosis of analog circuits: Taxonomy and state of the art KBS D. Binu AEU- International Journal of Electronics and Communications 73, 2017 | 121 | 2017 |
| Rider-deep-LSTM network for hybrid distance score-based fault prediction in analog circuits D Binu, BS Kariyappa IEEE Transactions on Industrial Electronics 68 (10), 10097-10106, 2020 | 81 | 2020 |
| Design and Development of Automatic Weed Detection and Smart Herbicide Sprayer Robot DMDBSK Aravind R International Conference on Recent Advances in Intellegent Computational …, 2015 | 61 | 2015 |
| Single Bit-line 7T SRAM cell for Low Power and High SNM Basavaraj Madiwalar and Dr. Kariyappa B S International Multi Conference on Automation, Computing, Control …, 2013 | 39* | 2013 |
| FPGA based speed control of AC servomotor using sinusoidal PWM MUK Kariyappa B S | 29 | 2008 |
| Automobile Black Box System for Accident Analysis KBS Monisha J Prasad International Conference on Advances in Electronics, Computers and …, 2014 | 27* | 2014 |
| Design and optimization of 8 bit ALU using reversible logic A Deeptha, D Muthanna, M Dhrithi, M Pratiksha, BS Kariyappa 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 23 | 2016 |
| Micro Controller Based Ac Power Controller. SAH Prasad, BS Kariyappa, R Nagaraj, SK Thakur Wirel. Sens. Netw. 1 (2), 76-81, 2009 | 19 | 2009 |
| A Comparative Study of 7T SRAM Cells MBM Dr. Kariyappa B S International Journal of Computer Trends and Technology (IJCTT) 4 (7), 2188, 2013 | 15 | 2013 |
| Design and implementation of 8-bit vedic multiplier using mGDI technique SS Meti, CN Bharath, YGP Kumar, BS Kariyappa 2017 International Conference on Advances in Computing, Communications and …, 2017 | 14 | 2017 |
| Implementation of power efficient 8-bit reversible linear feedback shift register for BIST YGP Kumar, BS Kariyappa, MZ Kurian 2017 International Conference on Inventive Systems and Control (ICISC), 1-5, 2017 | 13 | 2017 |
| Architecture Analysis and Verification of I3C Protocol A Mahale, BS Kariyappa 2019 3rd International conference on Electronics, Communication and …, 2019 | 12 | 2019 |
| Protocol implementation for Short Message Service over IP R D'Souza, BS Kariyappa, S Kumar, MU Kumari 2011 6th International Conference on Industrial and Information Systems, 443-447, 2011 | 12 | 2011 |
| PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories J Fadnavis, BS Kariyappa International Journal of Advanced Technology and Engineering Exploration 8 …, 2021 | 9 | 2021 |
| Performance analysis of multipliers using modified gate diffused input technology YG Praveen Kumar, BS Kariyappa, SM Shashank, CN Bharath IETE Journal of Research 68 (5), 3887-3899, 2022 | 8 | 2022 |
| Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique CSH Kumar, BS Kariyappa 2017 International Conference on Electrical, Electronics, Communication …, 2017 | 7 | 2017 |
| Position control of an AC servo motor using VHDL and FPGA BS Kariyappa, SA Hariprasad, R Nagaraj International Journal of Computer and Information Engineering 3 (1), 150-153, 2009 | 6 | 2009 |
| Node voltage and KCL model-based low leakage volatile and non-volatile 7T SRAM cells CSH Kumar, BS Kariyappa IETE Journal of Research 69 (10), 7227-7243, 2023 | 5 | 2023 |
| Digital twin ranorex test automation of SIPROTEC 5 protection devices K Asha, BS Kariyappa, V Kulakarni 2019 3rd International conference on Electronics, Communication and …, 2019 | 5 | 2019 |
Pawankumar BAssistant Professor , R. V. College of EngineeringDirección de correo verificada de rvce.edu.in