| Engineering negative differential resistance in NCFETs for analog applications H Agarwal, P Kushwaha, JP Duarte, YK Lin, AB Sachid, MY Kao, ... IEEE Transactions on Electron Devices 65 (5), 2033-2039, 2018 | 104 | 2018 |
| Proposal for capacitance matching in negative capacitance field-effect transistors H Agarwal, P Kushwaha, YK Lin, MY Kao, YH Liao, A Dasgupta, ... IEEE Electron Device Letters 40 (3), 463-466, 2019 | 87 | 2019 |
| Deep-learning-assisted physics-driven MOSFET current-voltage modeling MY Kao, H Kam, C Hu IEEE Electron Device Letters 43 (6), 974-977, 2022 | 65 | 2022 |
| BSIM compact model of quantum confinement in advanced nanosheet FETs A Dasgupta, SS Parihar, P Kushwaha, H Agarwal, MY Kao, S Salahuddin, ... IEEE Transactions on Electron Devices 67 (2), 730-737, 2020 | 56 | 2020 |
| Design optimization techniques in nanosheet transistor for RF applications P Kushwaha, A Dasgupta, MY Kao, H Agarwal, S Salahuddin, C Hu IEEE Transactions on Electron Devices 67 (10), 4515-4520, 2020 | 49 | 2020 |
| Analysis and modeling of inner fringing field effect on negative capacitance FinFETs YK Lin, H Agarwal, P Kushwaha, MY Kao, YH Liao, K Chatterjee, ... IEEE Transactions on Electron Devices 66 (4), 2023-2027, 2019 | 48 | 2019 |
| Spacer engineering in negative capacitance FinFETs YK Lin, H Agarwal, MY Kao, J Zhou, YH Liao, A Dasgupta, P Kushwaha, ... IEEE Electron Device Letters 40 (6), 1009-1012, 2019 | 46 | 2019 |
| NCFET design considering maximum interface electric field H Agarwal, P Kushwaha, YK Lin, MY Kao, YH Liao, JP Duarte, ... IEEE Electron Device Letters 39 (8), 1254-1257, 2018 | 46 | 2018 |
| Deep learning-based BSIM-CMG parameter extraction for 10-nm FinFET MY Kao, F Chavez, S Khandelwal, C Hu IEEE Transactions on Electron Devices 69 (8), 4765-4768, 2022 | 45 | 2022 |
| Variation caused by spatial distribution of dielectric and ferroelectric grains in a negative capacitance field-effect transistor MY Kao, AB Sachid, YK Lin, YH Liao, H Agarwal, P Kushwaha, JP Duarte, ... IEEE Transactions on Electron Devices 65 (10), 4652-4658, 2018 | 42 | 2018 |
| Characterization and modeling of flicker noise in FinFETs at advanced technology node P Kushwaha, H Agarwal, YK Lin, A Dasgupta, MY Kao, Y Lu, Y Yue, ... IEEE Electron Device Letters 40 (6), 985-988, 2019 | 40 | 2019 |
| BSIM-HV: High-voltage MOSFET model including quasi-saturation and self-heating effect H Agarwal, C Gupta, R Goel, P Kushwaha, YK Lin, MY Kao, JP Duarte, ... IEEE Transactions on Electron Devices 66 (10), 4258-4263, 2019 | 31 | 2019 |
| Neural network-based and modeling with high accuracy and potential model speed CT Tung, MY Kao, C Hu IEEE Transactions on Electron Devices 69 (11), 6476-6479, 2022 | 30 | 2022 |
| Strained Pseudomorphic Ge1–xSnx Multiple Quantum Well Microdisk Using SiNy Stressor Layer CS Fenrich, X Chen, R Chen, YC Huang, H Chung, MY Kao, Y Huo, ... ACS Photonics 3 (12), 2231-2236, 2016 | 29 | 2016 |
| Optimization of NCFET by matching dielectric and ferroelectric nonuniformly along the channel MY Kao, YK Lin, H Agarwal, YH Liao, P Kushwaha, A Dasgupta, ... IEEE Electron Device Letters 40 (5), 822-825, 2019 | 24 | 2019 |
| Effect of polycrystallinity and presence of dielectric phases on NC-FinFET variability YK Lin, MY Kao, H Agarwal, YH Liao, P Kushwaha, K Chatterjee, ... 2018 IEEE International Electron Devices Meeting (IEDM), 9.4. 1-9.4. 4, 2018 | 19 | 2018 |
| Modeling of advanced RF bulk FinFETs P Kushwaha, H Agarwal, YK Lin, MY Kao, JP Duarte, HL Chang, W Wong, ... IEEE Electron Device Letters 39 (6), 791-794, 2018 | 18 | 2018 |
| Analysis and modeling of polarization gradient effect on negative capacitance FET MY Kao, G Pahwa, A Dasgupta, S Salahuddin, C Hu IEEE Transactions on Electron Devices 67 (10), 4521-4525, 2020 | 17 | 2020 |
| Electric field-induced permittivity enhancement in negative-capacitance FET YH Liao, D Kwon, S Cheema, N Shanker, AJ Tan, MY Kao, LC Wang, ... IEEE Transactions on Electron Devices 68 (3), 1346-1351, 2021 | 13 | 2021 |
| Negative-capacitance FinFETs: Numerical simulation, compact modeling and circuit evaluation JP Duarte, YK Lin, YH Liao, A Sachid, MY Kao, H Agarwal, P Kushwaha, ... 2018 International conference on simulation of semiconductor processes and …, 2018 | 13 | 2018 |
chenming huUniversity of California, BerkeleyDirección de correo verificada de eecs.berkeley.edu