| Microarchitecture of Network-on-chip Routers G Dimitrakopoulos, A Psarras, I Seitanidis Springer, 2015 | 85 | 2015 |
| ShortPath: A network-on-chip router with fine-grained pipeline bypassing A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computers 65 (10), 3136-3147, 2016 | 49 | 2016 |
| PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation A Psarras, I Seitanidis, C Nicopoulos, G Dimitrakopoulos 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 44 | 2015 |
| ElastiStore: Flexible elastic buffering for virtual-channel-based networks on chip I Seitanidis, A Psarras, K Chrysanthou, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015 | 38 | 2015 |
| Elastistore: An elastic buffer architecture for network-on-chip routers I Seitanidis, A Psarras, G Dimitrakopoulos, C Nicopoulos 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 33 | 2014 |
| PhaseNoC: Versatile network traffic isolation through TDM-scheduled virtual channels A Psarras, J Lee, I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 31 | 2015 |
| ElastiNoC: A self-testable distributed VC-based network-on-chip architecture I Seitanidis, A Psarras, E Kalligeros, C Nicopoulos, G Dimitrakopoulos 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 135-142, 2014 | 22 | 2014 |
| Timing-driven and placement-aware multibit register composition I Seitanidis, G Dimitrakopoulos, PM Mattheakis, L Masse-Navette, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 15 | 2018 |
| Timing-driven placement optimization facilitated by timing-compatibility flip-flop clustering D Mangiras, A Stefanidis, I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 14 | 2019 |
| Automatic generation of peak-power traffic for networks-on-chip I Seitanidis, C Nicopoulos, G Dimitrakopoulos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 7 | 2018 |
| Timing driven incremental multi-bit register composition using a placement-aware ILP formulation I Seitanidis, G Dimitrakopoulos, P Mattheakis, L Masse-Navete, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 6 | 2017 |
| Hardware primitives for the synthesis of multithreaded elastic systems G Dimitrakopoulos, I Seitanidis, A Psarras, K Tsiouris, PM Mattheakis, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 6 | 2014 |
| Powermax: an automated methodology for generating peak-power traffic in networks-on-chip I Seitanidis, C Nicopoulos, G Dimitrakopoulos 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016 | 4 | 2016 |
| Low Power Networks-on-Chip I Seitanidis Δημοκρίτειο Πανεπιστήμιο Θράκης (ΔΠΘ). Σχολή Πολυτεχνική. Τμήμα Ηλεκτρολόγων …, 2018 | | 2018 |
Giorgos DimitrakopoulosProfessor, ECE, Democritus University of ThraceDirección de correo verificada de ee.duth.gr