| Fast and precise routability analysis with conditional design rules I Kang, D Park, C Han, CK Cheng Proceedings of the 20th System Level Interconnect Prediction Workshop, 1-8, 2018 | 25 | 2018 |
| Full MEMS monolithic microcolumn for wafer-level arrayal H Kim, C Han, J Kim, H Kim, K Chun Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2004 | 21 | 2004 |
| Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI C Han, AB Kahng, L Wang, B Xu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 20 | 2019 |
| Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI C Han, K Han, AB Kahng, H Lee, L Wang, B Xu 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 667-674, 2017 | 20 | 2017 |
| The novel deflector for multi arrayed microcolumn using microelectromechanical system (MEMS) technology H Kim, C Han, K Chun Japanese journal of applied physics 42 (6S), 4084, 2003 | 18 | 2003 |
| Semiconductor having cross coupled structure and layout verification method thereof T Song, JH Do, C Han US Patent 9,767,248, 2017 | 8 | 2017 |
| Monte Carlo simulation for analyzing yield of an electric circuit JY Lee, C Han US Patent 9,846,753, 2017 | 5* | 2017 |
| Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits C Han, T Kim Integration 78, 1-10, 2021 | 3 | 2021 |
| Computer based system for verifying layout of semiconductor device and layout verify method thereof C Han US Patent 10,095,825, 2018 | 2 | 2018 |
| Method and apparatus for fabricating semiconductor device HH Park, SW Choi, C Han US Patent 9,703,280, 2017 | 2 | 2017 |
| Method of calibrating target values and processing systems configured to calibrate the target values C Han, DW Kim, JY Lee, SW Choi, BH Kim, HH Park, S Choi, J Ku US Patent 9,613,002, 2017 | 2 | 2017 |
| New Interference Reduction Method Using the Vertical Ground Shield for Monolithic Microcolumn Array C Han, H Kim, J Cha, HC Kim, K Chun The 49th International Conference on Electron, Ion and Photon Beam …, 2005 | 2 | 2005 |
| Self-aligned carbon nanotubes for field emission tip with simple process B Eom, C Han, H Kim, M Yum, J Yang, C Park, K Chun 2006 First International Conference on Communications and Electronics, 497-499, 2006 | 1 | 2006 |
| Low energy electron beam lithography with microcolumn C Han, H Kim, J Kim, K Chun Digest of Papers. 2004 International Microprocesses and Nanotechnology …, 2004 | 1 | 2004 |
| The novel deflector for multi arrayed microcolumn using MEMS technology H Kim, C Han, K Chun 2002 International Microprocesses and Nanotechnology Conference, 2002 …, 2002 | 1 | 2002 |
| Integrated circuit including test circuit and method of manufacturing the same C Han, M Lim, Y Kim, K Oh US Patent 12,000,888, 2024 | | 2024 |
| Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based Library J Kim, C Han, C Bae, Y Kim, JH Kim, HS Seo 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-6, 2023 | | 2023 |
| Timing Analysis on Interconnects and Prediction on Design Rule Violations for Synthesizing Deep Sub-micron Circuits C Han | | 2021 |
| A miniaturized electron beam deflector and lens module with vertical interconnection using anodic bonding and Zn reflow C Han, B Eom, HC Kim, K Chun 2007 Digest of papers Microprocesses and Nanotechnology, 62-63, 2007 | | 2007 |
| Wafer Level Fabrication Method of Microcolumn Array for Improvement of Uniformity C Han, HC Kim, K Chun ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2006 | | 2006 |
