Systematic DC/AC performance benchmarking of sub-7-nm node FinFETs and nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek
IEEE Journal of the Electron Devices Society 6, 942-947, 2018
77 2018 Multi- Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing JS Yoon, J Jeong, S Lee, RH Baek
IEEE Journal of the Electron Devices Society 6, 861-865, 2018
62 2018 Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application J Jeong, JS Yoon, S Lee, RH Baek
IEEE Access 8, 35873-35881, 2020
42 2020 Bottom oxide bulk FinFETs without punch-through-stopper for extending toward 5-nm node JS Yoon, J Jeong, S Lee, RH Baek
IEEE Access 7, 75762-75767, 2019
37 2019 Sensitivity of source/drain critical dimension variations for sub-5-nm node fin and nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek
IEEE Transactions on Electron Devices 67 (1), 258-262, 2019
35 2019 Reduction of process variations for sub-5-nm node fin and nanosheet FETs using novel process scheme JS Yoon, S Lee, J Lee, J Jeong, H Yun, RH Baek
IEEE Transactions on Electron Devices 67 (7), 2732-2737, 2020
33 2020 Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications JS Yoon, J Jeong, S Lee, RH Baek
Japanese Journal of Applied Physics 58 (SB), SBBA12, 2019
31 2019 Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain JS Yoon, J Jeong, S Lee, RH Baek
IEEE Access 7, 38593-38596, 2019
30 2019 Metal source-/drain-induced performance boosting of sub-7-nm node nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek
IEEE Transactions on Electron Devices 66 (4), 1868-1873, 2019
27 2019 Digital/analog performance optimization of vertical nanowire FETs using machine learning JS Yoon, S Lee, H Yun, RH Baek
IEEE Access 9, 29071-29077, 2021
25 2021 Novel trench inner-spacer scheme to eliminate parasitic bottom transistors in silicon nanosheet FETs J Jeong, JS Yoon, S Lee, RH Baek
IEEE Transactions on Electron Devices 70 (2), 396-401, 2022
18 2022 Performance, power, and area of standard cells in sub 3 nm node using buried power rail JS Yoon, J Jeong, S Lee, J Lee, S Lee, RH Baek, SK Lim
IEEE Transactions on Electron Devices 69 (3), 894-899, 2022
17 2022 Neural network based design optimization of 14-nm node fully-depleted SOI FET for SoC and 3DIC applications H Yun, JS Yoon, J Jeong, S Lee, HC Choi, RH Baek
IEEE Journal of the Electron Devices Society 8, 1272-1280, 2020
17 2020 Source/drain patterning FinFETs as solution for physical area scaling toward 5-nm node JS Yoon, S Lee, J Lee, J Jeong, H Yun, B Kang, RH Baek
IEEE Access 7, 172290-172295, 2019
17 2019 Sensitivity of inner spacer thickness variations for sub-3-nm node silicon nanosheet field-effect transistors S Lee, J Jeong, JS Yoon, S Lee, J Lee, J Lim, RH Baek
Nanomaterials 12 (19), 3349, 2022
10 2022 TCAD-based flexible fin pitch design for 3-nm node 6T-SRAM using practical source/drain patterning scheme J Lee, JS Yoon, S Lee, J Jeong, RH Baek
IEEE Transactions on Electron Devices 68 (3), 1031-1036, 2021
8 2021 Gate-All-Around FETs: nanowire and nanosheet structure JS Yoon, J Jeong, S Lee, J Lee, RH Baek
Nanowires-recent progress, 2021
7 2021 DC performance variations by grain boundary in source/drain epitaxy of sub-3-nm nanosheet field-effect transistors JS Yoon, J Jeong, S Lee, J Lee, S Lee, J Lim, RH Baek
IEEE Access 10, 22032-22037, 2022
6 2022 Threshold Voltage Variations Induced by Si1− x Ge x and Si1− x Cx of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors J Jeong, JS Yoon, S Lee, RH Baek
Journal of Nanoscience and Nanotechnology 20 (8), 4684-4689, 2020
6 2020 Observation of mobility and velocity behaviors in ultra-scaled LG= 15 nm silicon nanowire field-effect transistors with different channel diameters S Lee, JS Yoon, J Jeong, J Lee, RH Baek
Solid-State Electronics 164, 107740, 2020
6 2020