| LeGO: A learning-guided obfuscation framework for hardware IP protection A Alaql, S Chattopadhyay, P Chakraborty, T Hoque, S Bhunia IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 17 | 2021 |
| A-QED verification of hardware accelerators E Singh, F Lonsing, S Chattopadhyay, M Strange, P Wei, X Zhang, Y Zhou, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 13 | 2020 |
| Machine learning assisted accurate estimation of usage duration and manufacturer for recycled and counterfeit flash memory detection S Chattopadhyay, P Kumari, B Ray, RS Chakraborty 2019 IEEE 28th Asian Test Symposium (ATS), 49-495, 2019 | 13 | 2019 |
| Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition S Chattopadhyay, F Lonsing, L Piccolboni, D Soni, P Wei, X Zhang, ... 2021 Formal Methods in Computer Aided Design (FMCAD), 42-52, 2021 | 4 | 2021 |
| A conditionally chaotic physically unclonable function design framework with high reliability S Chattopadhyay, P Santikellur, RS Chakraborty, J Mathew, M Ottavi ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (6 …, 2021 | 4 | 2021 |
| STT-MRAM for low power access for read-intensive parallel deep-learning architectures S Chattopadhyay, K Brahma, A Ray, M Sharad 2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017 | 3 | 2017 |
| Proof-Stitch: Proof Combination for Divide-and-Conquer SAT Solvers. AA Nair, S Chattopadhyay, H Wu, A Ozdemir, CW Barrett FMCAD, 84-88, 2022 | 2 | 2022 |
| G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators S Chattopadhyay, K Devarajegowda, B Zhao, F Lonsing, BA D’Agostino, ... 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 1 | 2023 |
| Learning guided obfuscation framework for hardware IP protection A Alaql, S Chattopadhyay, S Bhunia, P Chakraborty US Patent 11,341,283, 2022 | 1 | 2022 |
| QED and Symbolic QED: Dramatic Improvements in Pre-Silicon Verification and Post-Silicon Validation K Devarajegowda, F Lonsing, MR Fadiheh, S Chattopadhyay, D Lin, ... Foundations and Trends® in Integrated Circuits and Systems 3 (2–3), 51-217, 2024 | | 2024 |
| Cyclic Beneš Network Based Logic Encryption for Mitigating SAT-Based Attacks S Chattopadhyay, RS Chakraborty 2019 IEEE 37th International Conference on Computer Design (ICCD), 567-575, 2019 | | 2019 |
| A novel technique for implementing reactance in spin domain using Spin Hall Effect S Chattopadhyay Microelectronics Journal 79, 24-29, 2018 | | 2018 |
Rajat Subhra ChakrabortyProfessor, Dept. of Computer Science and Engineering, IIT Kharagpur, India - 721302Dirección de correo verificada de cse.iitkgp.ac.in