| A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496, 2018 | 361 | 2018 |
| Focal-plane-arrays and CMOS readout techniques of infrared imaging systems CC Hsieh, CY Wu, FW Jih, TP Sun IEEE Transactions on Circuits and Systems for Video Technology 7 (4), 594-605, 1997 | 298 | 1997 |
| 24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019 | 288 | 2019 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 251 | 2019 |
| 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020 | 244 | 2020 |
| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 222 | 2020 |
| CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors WH Chen, C Dou, KX Li, WY Lin, PY Li, JH Huang, JH Wang, WC Wei, ... Nature Electronics 2 (9), 420-428, 2019 | 222 | 2019 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 207 | 2019 |
| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 182 | 2020 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 177 | 2021 |
| 16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021 | 173 | 2021 |
| A 2.4-to-5.2 fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS CY Liou, CC Hsieh 2013 IEEE international solid-state circuits conference digest of technical …, 2013 | 150 | 2013 |
| A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu, TW Chang, HY Kao, ... Nature Electronics 4 (1), 81-90, 2021 | 132 | 2021 |
| A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS JY Lin, CC Hsieh IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 70-79, 2014 | 127 | 2014 |
| A 28nm 1Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6 ns latency, 1241GOPS and 37.01 TOPS/W for 8b-MAC operations for edge-AI devices PC Wu, JW Su, YL Chung, LY Hong, JS Ren, FC Chang, Y Wu, HY Chen, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 113 | 2022 |
| A new cryogenic CMOS readout structure for infrared focal plane array CC Hsieh, CY Wu, TP Sun IEEE Journal of Solid-State Circuits 32 (8), 1192-1199, 1997 | 100 | 1997 |
| Embedded 1-Mb ReRAM-based computing-in-memory macro with multibit input and weight for CNN-based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... IEEE Journal of Solid-State Circuits 55 (1), 203-215, 2019 | 99 | 2019 |
| A local computing cell and 6T SRAM-based computing-in-memory macro with 8-b MAC operation for edge AI chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... IEEE Journal of Solid-State Circuits 56 (9), 2817-2831, 2021 | 93 | 2021 |
| An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices JM Hung, YH Huang, SP Huang, FC Chang, TH Wen, CI Su, WS Khwa, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 92 | 2022 |
| A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC SE Hsieh, CC Hsieh IEEE Journal of Solid-State Circuits 53 (9), 2595-2603, 2018 | 92 | 2018 |