A 14 nm FinFET 128 Mb SRAM With V T Song, W Rim, J Jung, G Yang, J Park, S Park, Y Kim, KH Baek, S Baek, ...
IEEE Journal of Solid-State Circuits 50 (1), 158-169, 2014
192 2014 A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization T Song, W Rim, S Park, Y Kim, G Yang, H Kim, S Baek, J Jung, B Kwon, ...
IEEE Journal of Solid-State Circuits 52 (1), 240-249, 2016
122 2016 Methods of generating integrated circuit layout using standard cell library S Baek, JW Seo, G Yang, LEE Dal-Hee, S Cho
US Patent 9,460,259, 2016
34 2016 Semiconductor device including a gate electrode and a conductive structure JH Do, S Lee, J Jung, J Lim, G Yang, B Sanghoon, T Song
US Patent 10,541,243, 2020
28 2020 12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis T Song, H Kim, W Rim, Y Kim, S Park, C Park, M Hong, G Yang, J Do, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 208-209, 2017
18 2017 System-on-chip devices and methods of designing a layout therefor B Sanghoon, JH Do, T Song, G Yang, S Lee, J Lim
US Patent 9,646,960, 2017
17 2017 Semiconductor device and method for manufacturing the same JH Park, T Song, B Sanghoon, J Kim, G Yang, WON Hyosig
US Patent 9,536,946, 2017
14 2017 Design and algorithm for clock gating and flip-flop co-optimization G Yang, T Kim
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018
11 2018 Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semicondutor device using the same T Song, B Sanghoon, S Cho, JH Do, G Yang, J Lim
US Patent 9,928,333, 2018
11 2018 Method and system for designing semiconductor device S Baek, TJ Song, G Yang, DO Jeong-Ho
US Patent 9,842,182, 2017
7 2017 Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device KH Baek, JH Noh, TJ Song, G Yang, OH Sang-Kyu
US Patent 9,576,953, 2017
7 2017 3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology T Song, H Jung, G Yang, H Tang, H Kim, D Seo, H Kim, W Rim, S Baek, ...
2022 IEEE Custom Integrated Circuits Conference (CICC), 1-7, 2022
6 2022 Integrated circuit including standard cell I Kim, H Kim, TJ Song, JH Jung, G Yang, J Lim
US Patent 10,354,947, 2019
6 2019 Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process G Yang, H Jung, J Lim, J Seo, I Kim, J Yu, H You, J Kong, G Kim, M Jeong, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
3 2022 Semiconductor memory devices including a discharge circuit TJ Song, GH Kim, JH Park, GY Yang, JH Jung
US Patent 9,087,566, 2015
3 2015 Integrated circuit including integrated standard cell structure HG You, IG Kim, GY Yang, JS Yu, JY Lim, HC Jung
US Patent 11,244,961, 2022
2 2022 Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semiconductor device using the same T Song, B Sanghoon, S Cho, JH Do, G Yang, J Lim
US Patent 10,037,401, 2018
2 2018 Semiconductor device and method of manufacturing the same G Yang, I Kim
US Patent 11,741,285, 2023
1 2023 Adder cell and integrated circuit including the same SEO Jaewoo, M Jeong, Y Kim, G Yang, E Jun, C Kim, M Bae
US Patent App. 17/563,836, 2022
1 2022 Integrated circuit including standard cell I Kim, H Kim, TJ Song, JH Jung, G Yang, J Lim
US Patent 10,672,702, 2020
1 2020 
TAEJOONG SONGSamsung ElectronicsDirección de correo verificada de samsung.com
