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Ashwani Kumar Rana
Ashwani Kumar Rana
Associate Professor, NIT Hamirpur
Dirección de correo verificada de nith.ac.in
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Significance of nanotechnology in construction engineering
AK Rana, SB Rana, A Kumari, V Kiran
International Journal of Recent Trends in Engineering 1 (4), 46, 2009
1272009
A mathematical torque ripple minimization technique based on a nonlinear modulating factor for switched reluctance motor drives
AK Rana, AVR Teja
IEEE Transactions on Industrial Electronics 69 (2), 1356-1366, 2021
612021
Physical scaling limits of FinFET structure: A simulation study
G Saini, AK Rana
International Journal of VLSI design & communication Systems (VLSICS) 2 (1 …, 2011
552011
Impact of various parameters on the performance of free space optics communication system
N Kumar, AK Rana
Optik 124 (22), 5774-5776, 2013
502013
Impact of channel doping on dgmosfet parameters in nano regime-tcad simulation
VK Yadav, AK Rana
Int. J. Comput. Appl 37 (11), 36-41, 2012
382012
New low-power techniques: leakage feedback with stack & sleep stack with keeper
PK Pal, RS Rathore, AK Rana, G Saini
2010 International Conference on Computer and Communication Technology …, 2010
382010
Adiabatic technique for energy efficient logic circuits design
RK Yadav, AK Rana, S Chauhan, D Ranka, K Yadav
2011 International Conference on Emerging Trends in Electrical and Computer …, 2011
332011
Impact of air pollution on floral morphology of Cassia siamea Lamk.
SV Chauhan, B Chaurasia, A Rana
Journal of Environmental Biology 25 (3), 291-297, 2004
262004
A fault-tolerant power converter with multi-switch fault diagnosis and repair capability for 4-phase 8/6 SRM drives
AK Rana, AVR Teja
IEEE Transactions on Transportation Electrification 8 (3), 3896-3906, 2022
232022
Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects
S Kaushal, AK Rana
Superlattices and Microstructures 155, 106929, 2021
232021
Performance evaluation of FD-SOI MOSFETS for different metal gate work function
D Ranka, AK Rana, RK Yadav, K Yadav, D Giri
arXiv preprint arXiv:1104.0824, 2011
212011
Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design
RS Rathore, AK Rana
Superlattices and Microstructures 110, 68-81, 2017
202017
Four phase clocking rule for energy efficient digital circuits—An adiabatic concept
RK Yadav, AK Rana, S Chauhan, D Ranka, K Yadav
2011 2nd International Conference on Computer and Communication Technology …, 2011
192011
Negative capacitance junctionless FinFET for low power applications: an innovative approach
S Kaushal, AK Rana
Silicon 14 (12), 6719-6728, 2022
172022
Strained Si: Opportunities and challenges in nanoscale MOSFET
R Sharma, AK Rana
2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015
162015
An efficient 256-tap parallel FIR digital filter implementation using distributed arithmetic architecture
A Nandal, T Vigneswarn, AK Rana, A Dhaka
Procedia Computer Science 54, 605-611, 2015
162015
Performance analysis of FD-SOI MOSFET with different gate spacer dielectric
D Ranka, AK Rana, RK Yadav, D Giri
Int. J. Comput. Appl 18 (5), 22-27, 2011
162011
Leakage behavior of underlap FinFET structure: A simulation study
G Saini, AK Rana, PK Pal, S Jadav
2010 International Conference on Computer and Communication Technology …, 2010
162010
Analysis and evaluation of Si (1-x) Ge (x) pocket on sensitivity of a dual-material double-gate dopingless tunnel FET label-free biosensor
P Goma, AK Rana
Micro and Nanostructures 170, 207393, 2022
152022
Design and structural optimization of junctionless FinFET with Gaussian-doped channel
S Kaundal, AK Rana
Journal of Computational Electronics 17, 637-645, 2018
152018
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20