| MOSAIC: Mask optimizing solution with process window aware inverse correction JR Gao, X Xu, B Yu, DZ Pan Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 97 | 2014 |
| Self-aligned double patterning aware pin access and standard cell layout co-optimization X Xu, B Cline, G Yeric, B Yu, DZ Pan Proceedings of the 2014 on International symposium on physical design, 101-108, 2014 | 89 | 2014 |
| Computer implemented system and method for generating a layout of a cell defining a circuit component P De Dood, MW Frederick, JC Wang, BDN Lee, BT Cline, X Xu, AW Chen, ... US Patent 10,083,269, 2018 | 88 | 2018 |
| PARR: Pin access planning and regular routing for self-aligned double patterning X Xu, B Yu, JR Gao, CL Hsu, DZ Pan Proceedings of the 52nd Annual Design Automation Conference, 28, 2015 | 80 | 2015 |
| MrDP: Multiple-row detailed placement of heterogeneous-sized cells for advanced nodes Y Lin, B Yu, X Xu, JR Gao, N Viswanathan, WH Liu, Z Li, CJ Alpert, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 78 | 2017 |
| Methodology for standard cell compliance and detailed placement for triple patterning lithography B Yu, X Xu, JR Gao, Y Lin, Z Li, CJ Alpert, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 78 | 2015 |
| Standard cell library design and optimization methodology for ASAP7 PDK X Xu, N Shah, A Evans, S Sinha, B Cline, G Yeric 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 999 …, 2017 | 54 | 2017 |
| APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors Z Xie, X Xu, M Walker, J Knebel, K Palaniswamy, N Hebert, J Hu, H Yang, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 51 | 2021 |
| Design for manufacturability and reliability in extreme-scaling VLSI B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan Science China Information Sciences 59, 1-23, 2016 | 48 | 2016 |
| Net2: A graph attention network method customized for pre-placement net length estimation Z Xie, R Liang, X Xu, J Hu, Y Duan, Y Chen Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 46 | 2021 |
| A machine learning based framework for sub-resolution assist feature generation X Xu, T Matsunawa, S Nojima, C Kodama, T Kotani, DZ Pan Proceedings of the 2016 on International Symposium on Physical Design, 161-168, 2016 | 43 | 2016 |
| Pushing multiple patterning in sub-10nm: Are we ready? DZ Pan, L Liebmann, B Yu, X Xu, Y Lin Proceedings of the 52nd annual design automation conference, 1-6, 2015 | 43 | 2015 |
| New insights into AC RTN in scaled high-к/metal-gate MOSFETs under digital circuit operations J Zou, R Wang, N Gong, R Huang, X Xu, J Ou, C Liu, J Wang, J Liu, J Wu, ... 2012 Symposium on VLSI Technology (VLSIT), 139-140, 2012 | 43 | 2012 |
| Fast IR drop estimation with machine learning Z Xie, H Li, X Xu, J Hu, Y Chen Proceedings of the 39th international conference on computer-aided design, 1-8, 2020 | 38 | 2020 |
| Hierarchical and analytical placement techniques for high-performance analog circuits B Xu, S Li, X Xu, N Sun, DZ Pan Proceedings of the 2017 ACM on International Symposium on Physical Design, 55-62, 2017 | 35 | 2017 |
| A practical split manufacturing framework for trojan prevention via simultaneous wire lifting and cell insertion M Li, B Yu, Y Lin, X Xu, W Li, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 31 | 2018 |
| Subresolution assist feature generation with supervised data learning X Xu, Y Lin, M Li, T Matsunawa, S Nojima, C Kodama, T Kotani, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 29 | 2017 |
| Preplacement net length and timing estimation by customized graph neural network Z Xie, R Liang, X Xu, J Hu, CC Chang, J Pan, Y Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 28 | 2022 |
| Machine learning for mask/wafer hotspot detection and mask synthesis Y Lin, X Xu, J Ou, DZ Pan Photomask Technology 2017 10451, 72-84, 2017 | 28 | 2017 |
| Concurrent pin access optimization for unidirectional routing X Xu, Y Lin, V Livramento, DZ Pan Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 25 | 2017 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinDirección de correo verificada de ece.utexas.edu