Arrvindh Shriraman

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Sandhya DwarkadasWalter N. Munster Professor, Computer Science, University of VirginiaDirección de correo verificada de virginia.edu
Michael L. ScottArthur Gould Yates Professor, Computer Science, Univ. of RochesterDirección de correo verificada de cs.rochester.edu
Snehasish KumarGoogle, Simon Fraser UniversityDirección de correo verificada de sfu.ca
Michael SpearLehigh UniversityDirección de correo verificada de cse.lehigh.edu
Amirali SharifianCerebras SystemsDirección de correo verificada de cerebras.net
Apala GuhaLightmatterDirección de correo verificada de lightmatter.co
Kai ShenAssociate Professor of Computer Science, University of RochesterDirección de correo verificada de cs.rochester.edu
Nick SumnerAssociate Professor, Simon Fraser UniversityDirección de correo verificada de sfu.ca
Xiao ZhangGoogleDirección de correo verificada de google.com
Zhuan ChenMicrosoftDirección de correo verificada de microsoft.com
Mike O'ConnorNVIDIA ResearchDirección de correo verificada de nvidia.com
Wilson Wai Lun FungSamsungDirección de correo verificada de ece.ubc.ca
Tor M. AamodtProfessor, Electrical and Computer Engineering, University of British ColumbiaDirección de correo verificada de ece.ubc.ca
Luke DalessandroScientist, Indiana UniversityDirección de correo verificada de iu.edu
Lesley ShannonProfessor, School of Engineering Science, Simon Fraser UniversityDirección de correo verificada de ensc.sfu.ca
Parosh AbdullaProfessor of Computer Science, Uppsala UniversityDirección de correo verificada de it.uu.se
Ahmed RezineLinköping UniversityDirección de correo verificada de liu.se
Alexandra FedorovaProfessor of Computer Engineering, University of British ColumbiaDirección de correo verificada de ece.ubc.ca
Arun BharadwajSimon Fraser UniversityDirección de correo verificada de sfu.ca
niranjan soundararajanAMD

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Arrvindh Shriraman

Associate Professor of Computer Science

Dirección de correo verificada de cs.sfu.ca - Página principal

Computer Architecture Multiprocessors Synchronization Caches Hardware Accelerators


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
Cache coherence for GPU architectures I Singh, A Shriraman, WWL Fung, M O'Connor, TM Aamodt 2013 IEEE 19th International Symposium on High Performance Computer …, 2013	221	2013
Flexible decoupled transactional memory support A Shriraman, S Dwarkadas, ML Scott ACM SIGARCH Computer Architecture News 36 (3), 139-150, 2008	214	2008
An integrated hardware-software approach to flexible transactional memory A Shriraman, MF Spear, H Hossain, VJ Marathe, S Dwarkadas, ML Scott ACM SIGARCH Computer Architecture News 35 (2), 104-115, 2007	165	2007
Power containers: An OS facility for fine-grained power and energy management on multicore servers K Shen, A Shriraman, S Dwarkadas, X Zhang, Z Chen ACM SIGARCH Computer Architecture News 41 (1), 65-76, 2013	143	2013
Mechanism to support flexible decoupled transactional memory S Dwarkadas, A Shriraman, M Scott US Patent 8,661,204, 2014	132	2014
SPACE: Sharing pattern-based directory coherence for multicore scalability H Zhao, A Shriraman, S Dwarkadas Proceedings of the 19th international conference on Parallel architectures …, 2010	114	2010
Amoeba-cache: Adaptive blocks for eliminating waste in the memory hierarchy S Kumar, H Zhao, A Shriraman, E Matthews, S Dwarkadas, L Shannon 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 376-388, 2012	102	2012
Hardware acceleration of software transactional memory A Shriraman, VJ Marathe, S Dwarkadas, ML Scott, D Eisenstat, C Heriot, ... ACM SIGPLAN Workshop on Transactional Computing, Ottawa, ON, Canada, 2006	85	2006
SPATL: Honey, I shrunk the coherence directory H Zhao, A Shriraman, S Dwarkadas, V Srinivasan 2011 International Conference on Parallel Architectures and Compilation …, 2011	79	2011
Refereeing conflicts in hardware transactional memory A Shriraman, S Dwarkadas Proceedings of the 23rd international conference on Supercomputing, 136-146, 2009	72	2009
System and method for hardware acceleration of a software transactional memory M Scott, S Dwarkadas, A Shriraman, V Marathe, MF Spear US Patent 8,180,971, 2012	59	2012
SQRL: Hardware accelerator for collecting software data structures S Kumar, A Shriraman, V Srinivasan, D Lin, J Phillips Proceedings of the 23rd international conference on Parallel architectures …, 2014	52*	2014
Protozoa: Adaptive granularity cache coherence H Zhao, A Shriraman, S Kumar, S Dwarkadas ACM SIGARCH Computer Architecture News 41 (3), 547-558, 2013	52	2013
Spaghetti: Streaming accelerators for highly sparse gemm on fpgas R Hojabr, A Sedaghati, A Sharifian, A Khonsari, A Shriraman 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021	48	2021
Fusion: Design tradeoffs in coherent cache hierarchies for accelerators S Kumar, A Shriraman, N Vedula Proceedings of the 42Nd Annual International Symposium on Computer …, 2015	48	2015
Parabix: Boosting the efficiency of text processing on commodity processors D Lin, N Medforth, KS Herdy, A Shriraman, R Cameron IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012	44	2012
μir-an intermediate representation for transforming and optimizing the microarchitecture of application accelerators A Sharifian, R Hojabr, N Rahimi, S Liu, A Guha, T Nowatzki, A Shriraman Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019	42	2019
Bitwise data parallelism in regular expression matching RD Cameron, TC Shermer, A Shriraman, KS Herdy, D Lin, BR Hull, M Lin Proceedings of the 23rd international conference on Parallel architectures …, 2014	34	2014
TAPAS: Generating parallel accelerators from parallel programs S Margerm, A Sharifian, A Guha, A Shriraman, G Pokam 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018	32	2018
Transactional mutex locks MF Spear, A Shriraman, L Dalessandro, ML Scott SIGPLAN Workshop on Transactional Computing, 2009	32	2009

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