| Instrumenting AMS assertion verification on commercial platforms R Mukhopadhyay, SK Panda, P Dasgupta, J Gough ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 44 | 2009 |
| Optimizing test-generation to the execution platform A Nahir, A Ziv, S Panda 17th Asia and South Pacific Design Automation Conference, 304-309, 2012 | 19 | 2012 |
| Sliding mode control of gas turbines using multirate-output feedback S Panda, B Bandyopadhyay | 15 | 2008 |
| Efficient debugging of memory miscompare failures in post-silicon validation V Kolassery, G Kurucheti, SK Panda US Patent 9,336,100, 2016 | 7 | 2016 |
| Software-hardware adder SK Panda, N Vaish US Patent 8,825,727, 2014 | 5 | 2014 |
| Detecting missing write to cache/memory operations BD Budhabhatti, M Dusanapudi, S Kamaraju, V Mallikarjunan, SK Panda US Patent 9,287,005, 2016 | 4 | 2016 |
| A Framework for Systematic Validation and Debugging of Pipeline Simulators A Roy, SK Panda, R Kumar, PP Chakrabarti ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (3 …, 2005 | 3 | 2005 |
| A formal approach for specification-driven AMS behavioral model generation S Mukherjee, A Ain, SK Panda, R Mukhopadhyay, P Dasgupta 2009 Design, Automation & Test in Europe Conference & Exhibition, 1512-1517, 2009 | 2 | 2009 |
| Simulation-based verification using Temporally Attributed Boolean Logic SK Panda, A Roy, PP Chakrabarti, R Kumar ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (4 …, 2008 | 2 | 2008 |
| A static verification approach for architectural integration of mixed-signal integrated circuits R Mukhopadhyay, A Komuravelli, P Dasgupta, SK Panda, ... Integration 43 (1), 58-71, 2010 | 1 | 2010 |
| Chip stack cache extension with coherency ER Cordero, A Haridass, SK Panda, S Sethuraman, ... US Patent 9,252,131, 2016 | | 2016 |
| Leveraging accelerated simulation for floating-point regression J Paul, E Guralnik, A Koyfman, A Nahir, SK Panda Haifa Verification Conference, 118-131, 2012 | | 2012 |
| New Approaches for Simulation Based Verification of Pipelined Processors SK Panda IIT Kharagpur, 2010 | | 2010 |
| SystemC Modeling and Validation of A Pipelined RISC Processor Based System R Kumar, R Chaudhry, D Das, V Rathi, SK Panda, PP Chakrabarti | | |
Pallab DasguptaIndian Institute of Technology KharagpurDirección de correo verificada de cse.iitkgp.ac.in