| Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration KA Bowman, SG Duvall, JD Meindl IEEE Journal of solid-state circuits 37 (2), 183-190, 2002 | 994 | 2002 |
| Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ... IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008 | 457 | 2008 |
| A 45 nm resilient microprocessor core for dynamic variation tolerance KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ... IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010 | 341 | 2010 |
| A physical alpha-power law MOSFET model KA Bowman, BL Austin, JC Eble, X Tang, JD Meindl Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 218 | 1999 |
| Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance J Tschanz, K Bowman, S Walstra, M Agostinelli, T Karnik, V De 2009 Symposium on VLSI Circuits, 112-113, 2009 | 206 | 2009 |
| Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-core teraflops processor S Dighe, SR Vangal, P Aseron, S Kumar, T Jacob, KA Bowman, J Howard, ... IEEE Journal of Solid-State Circuits 46 (1), 184-193, 2010 | 185 | 2010 |
| Impact of parameter variations on circuits and microarchitecture OS Unsal, JW Tschanz, K Bowman, V De, X Vera, A Gonzalez, O Ergin Ieee Micro 26 (6), 30-39, 2006 | 170 | 2006 |
| Circuit techniques for dynamic variation tolerance K Bowman, J Tschanz, C Wilkerson, SL Lu, T Karnik, V De, S Borkar Proceedings of the 46th Annual Design Automation Conference, 4-7, 2009 | 169 | 2009 |
| Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance KA Bowman, X Tang, JC Eble, JD Menldl IEEE Journal of solid-state circuits 35 (8), 1186-1193, 2000 | 109 | 2000 |
| A minimum total power methodology for projecting limits on CMOS GSI AJ Bhavnagarwala, BL Austin, KA Bowman, JD Meindl IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (3), 235-251, 2000 | 103 | 2000 |
| Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 101 | 2008 |
| Variation-tolerant circuits: circuit solutions and techniques J Tschanz, K Bowman, V De Proceedings of the 42nd Annual Design Automation Conference, 762-763, 2005 | 89 | 2005 |
| PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010 | 85 | 2010 |
| Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) R Venkatesan, JA Davis, KA Bowman, JD Meindl IEEE transactions on very large scale integration (VLSI) systems 9 (6), 899-912, 2001 | 85 | 2001 |
| Impact of die-to-die and within-die parameter variations on the clock frequency and throughput of multi-core processors KA Bowman, AR Alameldeen, ST Srinivasan, CB Wilkerson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (12 …, 2009 | 84 | 2009 |
| A 22 nm all-digital dynamically adaptive clock distribution for supply voltage droop tolerance KA Bowman, C Tokunaga, T Karnik, VK De, JW Tschanz IEEE Journal of Solid-State Circuits 48 (4), 907-916, 2013 | 83 | 2013 |
| Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors KA Bowman, AR Alameldeen, ST Srinivasan, CB Wilkerson Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 79 | 2007 |
| A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance J Tschanz, K Bowman, SL Lu, P Aseron, M Khellah, A Raychowdhury, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 282-283, 2010 | 77 | 2010 |
| A 16 nm all-digital auto-calibrating adaptive clock distribution for supply voltage droop tolerance across a wide operating range KA Bowman, S Raina, JT Bridges, DJ Yingling, HH Nguyen, BR Appel, ... IEEE Journal of Solid-State Circuits 51 (1), 8-17, 2015 | 71 | 2015 |
| Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor S Dighe, S Vangal, P Aseron, S Kumar, T Jacob, K Bowman, J Howard, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 174-175, 2010 | 71 | 2010 |