| Invasive tightly-coupled processor arrays: A domain-specific architecture/compiler co-design approach F Hannig, V Lari, S Boppu, A Tanase, O Reiche ACM Transactions on Embedded Computing Systems (TECS) 13 (4s), 1-29, 2014 | 93 | 2014 |
| Symbolic parallelization of loop programs for massively parallel processor arrays J Teich, A Tanase, F Hannig 2013 IEEE 24th International Conference on Application-Specific Systems …, 2013 | 29 | 2013 |
| Symbolic mapping of loop programs onto processor arrays J Teich, A Tanase, F Hannig Journal of Signal Processing Systems 77, 31-59, 2014 | 22 | 2014 |
| A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays É Sousa, A Tanase, F Hannig, J Teich 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 20 | 2017 |
| Accuracy and performance analysis of harris corner computation on tightly-coupled processor arrays ÉR Sousa, A Tanase, F Hannig, J Teich 2013 Conference on Design and Architectures for Signal and Image Processing …, 2013 | 19 | 2013 |
| A co-design approach for fault-tolerant loop execution on coarse-grained reconfigurable arrays V Lari, A Tanase, J Teich, M Witterauf, F Khosravi, F Hannig, BH Meyer 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2015 | 14 | 2015 |
| A novel image impulse noise removal algorithm optimized for hardware accelerators VS Bhadouria, A Tanase, M Schmid, F Hannig, J Teich, D Ghoshal Journal of Signal Processing Systems 89, 225-242, 2017 | 12 | 2017 |
| Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays M Witterauf, A Tanase, F Hannig, J Teich 2016 IEEE 27th International Conference on Application-specific Systems …, 2016 | 12 | 2016 |
| Techniques for on-demand structural redundancy for massively parallel processor arrays V Lari, J Teich, A Tanase, M Witterauf, F Khosravi, BH Meyer Journal of Systems Architecture 61 (10), 615-627, 2015 | 11 | 2015 |
| Domain-specific augmentations for high-level synthesis M Schmid, A Tanase, F Hannig, J Teich, VS Bhadouria, D Ghoshal 2014 IEEE 25th International Conference on Application-Specific Systems …, 2014 | 11 | 2014 |
| High-level synthesis revised-Generation of FPGA accelerators from a domain-specific language using the polyhedron model M Schmid, F Hannig, A Tanase, J Teich Parallel Computing: Accelerating Computational Science and Engineering (CSE …, 2014 | 10 | 2014 |
| Orthogonal instruction processing: An alternative to lightweight VLIW processors M Brand, F Hannig, A Tanase, J Teich 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core …, 2017 | 8 | 2017 |
| On-demand fault-tolerant loop processing on massively parallel processor arrays A Tanase, M Witterauf, J Teich, F Hannig, V Lari 2015 IEEE 26th International Conference on Application-specific Systems …, 2015 | 8 | 2015 |
| Massively parallel processor architectures for resource-aware computing V Lari, A Tanase, F Hannig, J Teich arXiv preprint arXiv:1405.2907, 2014 | 8 | 2014 |
| Symbolic multi-level loop mapping of loop programs for massively parallel processor arrays A Tanase, M Witterauf, J Teich, F Hannig ACM Transactions on Embedded Computing Systems (TECS) 17 (2), 1-27, 2017 | 7 | 2017 |
| Providing fault tolerance through invasive computing V Lari, A Weichslgartner, A Tanase, M Witterauf, F Khosravi, J Teich, ... it-Information Technology 58 (6), 309-328, 2016 | 7 | 2016 |
| Adaptive fault tolerance through invasive computing M Witterauf, A Tanase, J Teich, V Lari, A Zwinkau, G Snelting 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2015 | 6 | 2015 |
| Symbolic inner loop parallelisation for massively parallel processor arrays A Tanase, M Witterauf, J Teich, F Hannig 2014 Twelfth ACM/IEEE Conference on Formal Methods and Models for Codesign …, 2014 | 6 | 2014 |
| Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays A Tanase, M Witterauf, J Teich, F Hannig 2015 ACM/IEEE International Conference on Formal Methods and Models for …, 2015 | 5 | 2015 |
| Acceleration of optical flow computations on tightly-coupled processor arrays ER Sousa, A Tanase, V Lari, F Hannig, J Teich, J Paul, W Stechele, ... Gesellschaft für Informatik eV, Fachgruppe PARS, 2013 | 5 | 2013 |
Frank HannigFriedrich-Alexander-Universität Erlangen-Nürnberg (FAU)ایمیل تأیید شده در cs.fau.de