PanGu- : Large-scale Autoregressive Pretrained Chinese Language Models with Auto-parallel Computation W Zeng, X Ren, T Su, H Wang, Y Liao, Z Wang, X Jiang, ZZ Yang, K Wang, ...
arXiv preprint arXiv:2104.12369, 2021
250 2021 Pre-training on Large-Scale Heterogeneous Graph X Jiang, T Jia, Y Fang, C Shi, Z Lin, H Wang
Proceedings of the 27th ACM SIGKDD Conference on Knowledge Discovery & Data …, 2021
51 2021 HL-Pow: A learning-based power modeling framework for high-level synthesis Z Lin, J Zhao, S Sinha, W Zhang
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 574-580, 2020
39 2020 Towards efficient and scalable acceleration of online decision tree learning on FPGA Z Lin, S Sinha, W Zhang
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
21 2019 PowerGear: Early-stage power estimation in FPGA HLS via heterogeneous edge-centric GNNs Z Lin, Z Yuan, J Zhao, W Zhang, H Wang, Y Tian
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
17 2022 An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
16 2018 Hard-odt: Hardware-friendly online decision tree learning algorithm and system Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
11 2020 Decision tree based hardware power monitoring for run time dynamic power management in FPGA Z Lin, W Zhang, S Sharad
2017 27th International Conference on Field Programmable Logic and …, 2017
11 2017 Scalable light-weight integration of fpga based accelerators with chip multi-processors Z Lin, S Sinha, H Liang, L Feng, W Zhang
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 152-162, 2017
6 2017 AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs M Gao, J Zhao, Z Lin, W Ding, X Hou, Y Feng, C Li, M Guo
2024 IEEE 42nd International Conference on Computer Design (ICCD), 162-169, 2024
5 2024 Mars: Exploiting multi-level parallelism for dnn workloads on adaptive multi-accelerator systems G Shen, J Zhao, Z Wang, Z Lin, W Ding, C Wu, Q Chen, M Guo
2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023
4 2023 Improving gpu energy efficiency through an application-transparent frequency scaling policy with performance assurance Y Zhang, Q Wang, Z Lin, P Xu, B Wang
Proceedings of the Nineteenth European Conference on Computer Systems, 769-785, 2024
2 2024 HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS Z Lin, T Liang, J Zhao, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
2 2023 GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network C Su, L Du, T Liang, Z Lin, M Wang, S Sinha, W Zhang
Proceedings of the 2024 ACM/SIGDA International Symposium on Field …, 2024
1 2024 Hierarchical source-to-post-route qor prediction in high-level synthesis with gnns M Gao, J Zhao, Z Lin, M Guo
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024
1 2024 Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator J Peng, T Liang, J Jiang, Y Zhang, Z Lin, Z Xie, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
2024 Array Partitioning Method for Streaming Dataflow Optimization in High-level Synthesis R Hou, J Zhai, Y Wang, Z Lin, K Zhao
2024 2nd International Symposium of Electronics Design Automation (ISEDA …, 2024
2024 Learning-based power modeling for FPGA: from design time to run time Z Lin
Hong Kong University of Science and Technology, 2019
2019