| A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator S Byun, CH Park, Y Song, S Wang, CSG Conroy, B Kim IEEE Journal of Solid-State Circuits 38 (10), 1609-1618, 2003 | 68 | 2003 |
| A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector S Byun, JC Lee, JH Shim, K Kim, HK Yu IEEE journal of solid-state circuits 41 (11), 2566-2576, 2006 | 66 | 2006 |
| A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer J Kim, J Yang, S Byun, H Jun, J Park, CSG Conroy, B Kim IEEE Journal of Solid-State Circuits 40 (2), 462-471, 2005 | 56 | 2005 |
| DLL with false lock protector SJ Byun, B Kim, CH Park US Patent 6,844,761, 2005 | 33 | 2005 |
| Charge pump circuit for a PLL SJ Byun, B Kim, CH Park US Patent 6,952,126, 2005 | 26 | 2005 |
| Analysis and Design of CMOS Received Signal Strength Indicator S Byun IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2970-2977, 2014 | 23 | 2014 |
| Digital linear amplification with nonlinear components (LINC) transmitter S Byun, K Kim, K Lim, CH Lee, H Kim, J Laskar US Patent 7,889,811, 2011 | 23 | 2011 |
| A 600MHz CMOS OFDM LINC transmitter with a 7 bit digital phase modulator KW Kim, S Byun, K Lim, CH Lee, J Laskar 2008 IEEE Radio Frequency Integrated Circuits Symposium, 677-680, 2008 | 20 | 2008 |
| A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector S Byun IEEE Transactions on Circuits and Systems I: Regular Papers 63 (10), 1592-1604, 2016 | 19 | 2016 |
| On frequency detection capability of full-rate linear and binary phase detectors CH Son, S Byun IEEE Transactions on Circuits and Systems II: Express Briefs 64 (7), 757-761, 2017 | 12 | 2017 |
| Clock and data recovery circuit SJ Byun US Patent 8,699,649, 2014 | 12 | 2014 |
| A quad-channel 3.125 Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18/spl mu/m CMOS J Yang, J Kim, S Byun, C Conroy, B Kim 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 12 | 2004 |
| 1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector S Byun, CH Son, J Hwang, BH Min, MY Park, HK Yu IET Circuits, Devices & Systems 7 (3), 159-168, 2013 | 10 | 2013 |
| A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 CMOS Technology BG Kim, LS Kim, S Byun, HK Yu IEEE journal of solid-state circuits 43 (2), 541-549, 2008 | 10 | 2008 |
| Categorization and characterization of time domain CMOS temperature sensors S Byun Sensors 20 (22), 6700, 2020 | 9 | 2020 |
| A 20Gb/s 1: 4 DEMUX without inductors in 0.13 um CMOS BG Kim, LS Kim, S Byun, HK Yu 2006 IEEE International Solid-State Circuits Conference, ISSCC, 2006 | 9 | 2006 |
| A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator CH Park, S Byun, Y Song, S Wang, C Conroy, B Kim 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of …, 2003 | 9 | 2003 |
| Frequency lock detector SJ Byun, HK Yu US Patent 7,643,598, 2010 | 7 | 2010 |
| LC quadrature VCO having startup circuit SJ Byun, CS Kim US Patent 7,436,266, 2008 | 6 | 2008 |
| Replica bias circuit SJ Byun, HK Yu US Patent 7,429,874, 2008 | 6 | 2008 |