| Review of the nanoscale FinFET device for the applications in nano-regime SU Haq, VK Sharma Current Nanoscience 19 (5), 651-662, 2023 | 15 | 2023 |
| Energy-efficient high-speed dynamic logic-based one-trit multiplier in CNTFET technology SU Haq, E Abbasian, VK Sharma, T Khurshid, H Fathi AEU-International Journal of Electronics and Communications 175, 155088, 2024 | 11 | 2024 |
| Ternary encoder and decoder designs in RRAM and CNTFET technologies SU Haq, VK Sharma e-Prime-Advances in Electrical Engineering, Electronics and Energy 7, 100397, 2024 | 8 | 2024 |
| Robust logic circuits design using SOI shorted-gate FinFETs SU Haq, VK Sharma Indian Journal of Pure & Applied Physics (IJPAP) 61 (01), 57-66, 2023 | 7 | 2023 |
| Energy-efficient design for logic circuits using a leakage control configuration in FinFET technology S Ul Haq, VK Sharma Journal of The Institution of Engineers (India): Series B 105 (4), 903-911, 2024 | 4 | 2024 |
| Energy-efficient CNTFET-RRAM based ternary logic design SU Haq, VK Sharma 2023 3rd International Conference on Advancement in Electronics …, 2023 | 4 | 2023 |
| Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology S ul Haq, E Abbasian, T Khurshid, VK Sharma Physica Scripta 99 (6), 065938, 2024 | 3 | 2024 |
| Improved stability for robust and low-power SRAM cell using FinFET technology SU Haq, VK Sharma Journal of Circuits, Systems and Computers 33 (06), 2450106, 2024 | 3 | 2024 |
| Tri-state GNRFET-based fast and energy-efficient ternary multiplier SU Haq, E Abbasian, T Khurshid, H Fathi, VK Sharma AEU-International Journal of Electronics and Communications 177, 155239, 2024 | 3 | 2024 |
| Reliable and ultra-low power approach for designing of logic circuits SU Haq, VK Sharma Analog Integrated Circuits and Signal Processing 119 (1), 85-95, 2024 | 3 | 2024 |
| Challenges in low power VLSI design: a review SU Haq, VK Sharma 2021 5th International Conference on Electronics, Communication and …, 2021 | 3 | 2021 |
| Modified on-off logic technique for low leakage CMOS circuits VK Sharma, S Ul Haq Journal of Nanoelectronics and Optoelectronics 13 (1), 55-67, 2018 | 3 | 2018 |
| Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology S ul Haq, E Abbasian, T Khurshid, VK Sharma Physica Scripta 99 (8), 085119, 2024 | 2 | 2024 |
| Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs S ul Haq, E Abbasian, T Khurshid, SJ Basha, VK Sharma Physica Scripta 99 (8), 085237, 2024 | 2 | 2024 |
| CNTFET-based Multiplexer Unit using INDEP Method M Maqbool, SU Haq, VK Sharma 2023 International Conference on Sustainable Computing and Smart Systems …, 2023 | 2 | 2023 |
| FinFET-based low-power improved PDP 4: 2 approximate compressor design SU Haq, VK Sharma J. Circuits Syst. Comput., 2450253, 2024 | 1 | 2024 |
| A Low Leakage Variations and High Stability 9T SRAM Cells SUIH Guguloth Anjaneyulu, M Durga Prakash, Mukku Pavan Kumar IEEE Electron Devices Kolkata Conference (EDKCON), 1-25, 2025 | | 2025 |
| An efficient design methodology for a tri-state multiplier circuit in carbon nanotube technology SU Haq, M Orouji, T Khurshid, E Abbasian Physica Scripta 100 (1), 015008, 2024 | | 2024 |
| A Low Leakage Variations and High Stability 9T SRAM Cells G Anjaneyulu, MD Prakash, MP Kumar, SU Haq 2024 IEEE International Conference of Electron Devices Society Kolkata …, 2024 | | 2024 |
| An Approach for Low Power Circuit Design Using Low Threshold Transistors. S UL HAQ, VK SHARMA Journal of Active & Passive Electronic Devices 14, 2019 | | 2019 |