| Time-interleaved SAR ADC with background timing-skew calibration for UWB wireless communication in IoT systems K Seong, DK Jung, DH Yoon, JS Han, JE Kim, TTH Kim, W Lee, KH Baek Sensors 20 (8), 2430, 2020 | 17 | 2020 |
| Design and analysis of low power and high SFDR direct digital frequency synthesizer JM Choi, DH Yoon, DK Jung, K Seong, JS Han, W Lee, KH Baek IEEE Access 8, 67581-67590, 2020 | 14 | 2020 |
| A 0.5 V 8–12 Bit 300 kSps SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations JE Kim, T Yoo, DK Jung, DH Yoon, K Seong, TTH Kim, KH Baek IEEE Access 8, 101359-101368, 2020 | 11 | 2020 |
| A 0.5 V 10 b 3 MS/s 2-then-1b/cycle SAR ADC with digital-based time-domain reference and dual-mode comparator DK Jung, K Seong, JS Han, Y Shim, KH Baek IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 909-913, 2021 | 10 | 2021 |
| A 2.5 GS/s 7-Bit 5-way time-interleaved SAR ADC with on-chip background offset and timing-skew calibration K Seong, JS Han, Y Shim, KH Baek IEEE Transactions on Circuits and Systems II: Express Briefs 69 (10), 4043-4047, 2022 | 8 | 2022 |
| 8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation KY Chung, H Kim, Y An, K Seong, DH Shin, KH Baek, Y Shim IEEE Access 12, 24254-24261, 2024 | 2 | 2024 |
| A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier DH Yoon, DK Jung, K Seong, JS Han, KY Chung, JE Kim, TTH Kim, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (7), 915-925, 2022 | 2 | 2022 |
| A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement DH Yoon, DK Jung, K Seong, TH Eom, JS Han, JE Kim, TTH Kim, ... 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 2 | 2021 |
| A reference-sampling based calibration-free fractional-N PLL with a PI-linked sampling clock generator JS Han, TH Eom, SW Choi, K Seong, DH Yoon, TTH Kim, KH Baek, ... Sensors 21 (20), 6824, 2021 | 2 | 2021 |
| An Area-Efficient Dual-Mode SAR ADC With 3-Level Analog Prediction to Compensate for Input Range Loss of Mismatch Error Shaping K Seong, JT Seo, J Lee, S Lee, TTH Kim, KH Baek 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 649-652, 2024 | | 2024 |
| A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs K Seong, JS Han, SE Kim, Y Shim, KH Baek Journal of Semiconductor Technology and Science 22 (6), 436-451, 2022 | | 2022 |
| Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems SW Choi, K Seong, S Lee, KH Baek, Y Shim Electronics 11 (4), 577, 2022 | | 2022 |
| Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems. Electronics 2022, 11, 577 SW Choi, K Seong, S Lee, KH Baek, Y Shim s Note: MDPI stays neu-tral with regard to jurisdictional claims in …, 2022 | | 2022 |
| A 12-bit DAC with DEM Technique for over 60dBc SFDR BK Choi, K Seong, W Lee, KH Baek 대한전자공학회 학술대회, 144-146, 2019 | | 2019 |
| Double Rail-to-Rail NTV SAR ADC YJ Jo, K Seong, IS Seo, KH Baek Journal of IKEEE 22 (4), 1218-1221, 2018 | | 2018 |
Tony Tae-Hyoung KIMAssociate Professor, Nanyang Technological Universityایمیل تأیید شده در ntu.edu.sg
