| Extreme environment electronics JD Cressler, HA Mantooth CRC Press, 2017 | 294 | 2017 |
| Comparison of combinational and sequential error rates for a deep submicron process NN Mahatme, S Jagannathan, TD Loveless, LW Massengill, BL Bhuva, ... IEEE Transactions on Nuclear Science 58 (6), 2719-2725, 2011 | 187 | 2011 |
| Neutron-and proton-induced single event upsets for D-and DICE-flip/flop designs at a 40 nm technology node TD Loveless, S Jagannathan, T Reece, J Chetia, BL Bhuva, MW McCurdy, ... IEEE Transactions on Nuclear Science 58 (3), 1008-1014, 2011 | 177 | 2011 |
| A hardened-by-design technique for RF digital phase-locked loops TD Loveless, LW Massengill, BL Bhuva, WT Holman, AF Witulski, ... IEEE transactions on nuclear science 53 (6), 3432-3438, 2006 | 144 | 2006 |
| A single-event-hardened phase-locked loop fabricated in 130 nm CMOS TD Loveless, LW Massengill, BL Bhuva, WT Holman, RA Reed, ... IEEE transactions on nuclear science 54 (6), 2012-2020, 2007 | 137 | 2007 |
| Modeling and mitigating single-event transients in voltage-controlled oscillators TD Loveless, LW Massengill, WT Holman, BL Bhuva IEEE Transactions on Nuclear Science 54 (6), 2561-2567, 2007 | 118 | 2007 |
| Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology K Lilja, M Bounasser, SJ Wen, R Wong, J Holst, N Gaspard, ... IEEE Transactions on Nuclear Science 60 (4), 2782-2788, 2013 | 112 | 2013 |
| Technology scaling and soft error reliability LW Massengill, BL Bhuva, WT Holman, ML Alles, TD Loveless 2012 IEEE International Reliability Physics Symposium (IRPS), 3C. 1.1-3C. 1.7, 2012 | 111 | 2012 |
| Radio identity verification-based IoT security using RF-DNA fingerprints and SVM D Reising, J Cancelleri, TD Loveless, F Kandah, A Skjellum IEEE Internet of Things Journal 8 (10), 8356-8371, 2020 | 77 | 2020 |
| Impact of technology scaling on the combinational logic soft error rate NN Mahatme, NJ Gaspard, T Assis, S Jagannathan, I Chatterjee, ... 2014 IEEE international reliability physics symposium, 5F. 2.1-5F. 2.6, 2014 | 73 | 2014 |
| A probabilistic analysis technique applied to a radiation-hardened-by-design voltage-controlled oscillator for mixed-signal phase-locked loops TD Loveless, LW Massengill, BL Bhuva, WT Holman, MC Casey, ... IEEE Transactions on Nuclear Science 55 (6), 3447-3455, 2008 | 68 | 2008 |
| Single-event tolerant flip-flop design in 40-nm bulk CMOS technology S Jagannathan, TD Loveless, BL Bhuva, SJ Wen, R Wong, M Sachdev, ... IEEE Transactions on Nuclear Science 58 (6), 3033-3037, 2011 | 67 | 2011 |
| Frequency dependence of alpha-particle induced soft error rates of flip-flops in 40-nm CMOS technology S Jagannathan, TD Loveless, BL Bhuva, NJ Gaspard, N Mahatme, ... IEEE Transactions on Nuclear Science 59 (6), 2796-2802, 2012 | 64 | 2012 |
| Impact of supply voltage and frequency on the soft error rate of logic circuits NN Mahatme, NJ Gaspard, S Jagannathan, TD Loveless, BL Bhuva, ... IEEE Transactions on Nuclear Science 60 (6), 4200-4206, 2013 | 59 | 2013 |
| On-chip measurement of single-event transients in a 45 nm silicon-on-insulator technology TD Loveless, JS Kauppila, S Jagannathan, DR Ball, JD Rowe, ... IEEE Transactions on Nuclear Science 59 (6), 2748-2755, 2012 | 58 | 2012 |
| Radiation hardness of FDSOI and FinFET technologies ML Alles, RD Schrimpf, RA Reed, LW Massengill, RA Weller, ... IEEE 2011 International SOI Conference, 1-2, 2011 | 56 | 2011 |
| Technology scaling comparison of flip-flop heavy-ion single-event upset cross sections NJ Gaspard, S Jagannathan, ZJ Diggins, MP King, SJ Wen, R Wong, ... IEEE Transactions on Nuclear Science 60 (6), 4368-4373, 2013 | 55 | 2013 |
| A generalized linear model for single event transient propagation in phase-locked loops TD Loveless, LW Massengill, WT Holman, BL Bhuva, D McMorrow, ... IEEE Transactions on Nuclear Science 57 (5), 2933-2947, 2010 | 54 | 2010 |
| Automated identification of electrical disturbance waveforms within an operational smart power grid AJ Wilson, DR Reising, RW Hay, RC Johnson, AA Karrar, TD Loveless IEEE Transactions on Smart Grid 11 (5), 4380-4389, 2020 | 43 | 2020 |
| Utilizing device stacking for area efficient hardened SOI flip-flop designs JS Kauppila, TD Loveless, RC Quinn, JA Maharrey, ML Alles, ... 2014 IEEE International Reliability Physics Symposium, SE. 4.1-SE. 4.7, 2014 | 43 | 2014 |