A fully-synthesizable fractional-N injection-locked PLL for digital clocking with triangle/sawtooth spread-spectrum modulation capability in 5-nm CMOS B Liu, Y Zhang, J Qiu, H Huang, Z Sun, D Xu, H Zhang, Y Wang, J Pang, ...
IEEE Solid-State Circuits Letters 3, 34-37, 2020
28 2020 A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth J Qiu, Z Sun, B Liu, W Wang, D Xu, H Herdian, H Huang, Y Zhang, ...
IEEE Journal of Solid-State Circuits 56 (12), 3741-3755, 2021
26 2021 A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch Z Sun, H Liu, H Huang, D Tang, D Xu, T Kaneko, Z Li, J Pang, R Wu, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 196-209, 2020
14 2020 10.3 A 7GHz DIGITAL PLL with cascaded fractional divider and pseudo-differential DTC achieving-62.1 dBc fractional spur and 143.7 fs integrated jitter D Xu, Z Liu, Y Kuai, H Huang, Y Zhang, Z Sun, B Liu, W Wang, Y Xiong, ...
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 192-194, 2024
13 2024 A 6.5-to-8GHz cascaded dual-fractional-N digital PLL achieving-63.7 dBc fractional spurs with 50MHz reference D Xu, Y Zhang, H Huang, Z Sun, B Liu, AA Fadila, J Qiu, Z Liu, W Wang, ...
2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023
12 2023 Investigation of exciton recombination zone in quantum dot light-emitting diodes using a fluorescent probe X Huang, H Zhang, D Xu, F Wen, S Chen
ACS Applied Materials & Interfaces 9 (33), 27809-27816, 2017
11 2017 A 32kHz-reference 2.4 GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration J Qiu, W Wang, Z Sun, B Liu, Y Zhang, D Xu, H Huang, AA Fadila, Z Liu, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 80-82, 2023
8 2023 A 78 fs RMS jitter injection-locked clock multiplier using transformer-based ultra-low-power VCO Z Sun, H Liu, D Xu, H Huang, B Liu, Z Li, J Pang, T Someya, A Shirane
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
3 2019 A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range H Huáng, B Liu, Z Liu, D Xu, Y Zhang, W Madany, J Qiu, Z Sun, AA Fadila, ...
IEEE Solid-State Circuits Letters 7, 54-57, 2024
2 2024 A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration Z Sun, D Xu, J Qiu, Z Liu, Y Zhang, H Huang, H Liu, B Liu, Z Li, J Pang, ...
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
2 2021 A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond Y Zhang, M Tang, J Pang, Z Li, D Xu, D Xu, Y Zhang, K Kunihiro, H Sakai, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
1 2024 A time-mode-modulation digital quadrature power amplifier based on 1-bit delta-sigma modulator and transformer combined FIR FIlter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ...
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023
1 2023 A Low-Jitter Injection-Locked Clock Multiplier Using 97-µW Transformer-Based VCO with 18-kHz Flicker Noise Corner Z Sun, H Liu, D Xu, H Huang, B Liu, Z Li, J Pang, T Someya, A Shirane, ...
IEICE Transactions on Electronics 104 (7), 289-299, 2021
1 2021 A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications Z Sun, D Xu, H Huang, Z Li, H Liu, B Liu, J Pang, T Someya, A Shirane, ...
IEICE Transactions on Electronics 103 (10), 505-513, 2020
1 2020 A 640-Gb/s 4 4-MIMO D-Band CMOS Transceiver Chipset C Liu, Z Li, Y Yamazaki, H Herdian, C Wang, A Tian, J Sakamaki, H Nie, ...
IEEE Journal of Solid-State Circuits, 2024
2024 A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a 62.1-dBc Fractional Spur D Xu, Z Liu, Y Kuai, H Huang, Y Zhang, Z Sun, B Liu, W Wang, Y Xiong, ...
IEEE Journal of Solid-State Circuits, 2024
2024 Digital Phase-Locked Loops: Exploring Different Boundaries Y Zhang, D Xu, K Okada
IEEE Open Journal of the Solid-State Circuits Society, 2024
2024 A 6.5-to-8-GHz Cascaded Dual-Fractional- Digital PLL Achieving 52.79-dBc Fractional Spur With 50-MHz Reference D Xu, Y Zhang, H Huang, Z Sun, B Liu, AA Fadila, J Qiu, Z Liu, W Wang, ...
IEEE Journal of Solid-State Circuits, 2024
2024 A VCO With Robust Implicit Common-Mode Resonance Against Nonideal Decoupling Network D Xu, Z Sun, Y Xiong, Y Zhang, H Huang, Z Liu, AA Fadila, A Shirane, ...
IEEE Solid-State Circuits Letters, 2024
2024 A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ...
IEEE Journal of Solid-State Circuits 59 (4), 993-1005, 2024
2024