| Design space exploration of low-power flip-flops in FinFET technology E Mahmoodi, M Gholipour Integration 75, 52-62, 2020 | 21 | 2020 |
| An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3: 1 multiplexers in 32‐nm GNRFET technology E Abbasian, M Orouji, S Taghipour Anvari, A Asadi, E Mahmoodi International Journal of Circuit Theory and Applications 51 (10), 4969-4983, 2023 | 16 | 2023 |
| Analysis and Evaluation of the Effect of Design Parameters on Timing Parameters and Power Consumption of Static Flip-Flop in 16 nm Technology Node E Mahmoodi, M Gholipour Nashriyyah-i Muhandisi-i Barq va Muhandisi-i Kampyutar-i Iran 72 (2), 145, 2019 | | 2019 |
| Study of transistor sizing techniques for low-power design in FinFET technology E Mahmoodi, M Gholipour Low Power Designs in Nanodevices and Circuits for Emerging Applications, 67-84, 0 | | |
| تحليل و بررسي تأثير پارامترهاي طراحي فليپ فلاپ استاتيک بر مشخصه هاي زماني و توان مصرفي آن در تکنولوژي 16 نانومتر محمودي احسان, قلي پور مرتضي مهندسي برق و مهندسي کامپيوتر ايران-ب مهندسي كامپيوتر 17 (2), 145-152, 0 | | |
Morteza GholipourBabol Noshirvani University of TechnologyVahvistettu sähköpostiosoite verkkotunnuksessa nit.ac.ir