| Basic-set trellis min–max decoder architecture for nonbinary ldpc codes with high-order galois fields HP Thi, H Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 496-507, 2017 | 30 | 2017 |
| Two-extra-column trellis min–max decoder architecture for nonbinary LDPC codes HP Thi, H Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (5 …, 2017 | 22 | 2017 |
| Parallel block-layered nonbinary QC-LDPC decoding on GPU HT Pham, S Ajaz, H Lee 2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015 | 11 | 2015 |
| Efficient Min-Max nonbinary LDPC decoding on GPU HP Thi, S Ajaz, H Lee 2014 International SoC Design Conference (ISOCC), 266-267, 2014 | 9 | 2014 |
| High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes HP Thi, S Ajaz, H Lee Integration 59, 52-63, 2017 | 6 | 2017 |
| Reduced-complexity trellis min-max decoder for non-binary LDPC codes HP Thi, H Lee 2018 IEEE International Conference on Acoustics, Speech and Signal …, 2018 | 3 | 2018 |
| Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes HP Thi, H Lee, XN Pham Integration 69, 234-241, 2019 | 1 | 2019 |
| High-Throughput Multi-Threaded Non-binary LDPC Decoder Architecture TX Pham, TN Tan, P Duong-Ngoc, HP Thi, H Lee 한국차세대컴퓨팅학회 학술대회, 374-376, 2021 | | 2021 |
| ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE HP Thi, HD Tuan, NP Xuan Journal of Computer Science and Cybernetics 37 (2), 91-106, 2021 | | 2021 |
| Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder HP Thi, CD The, NP Xuan, HD Tuan, H Lee 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 213-216, 2019 | | 2019 |
| Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding HP Thi, HD Tuan, H Lee, TN Huu 2018 International Conference on Advanced Technologies for Communications …, 2018 | | 2018 |
| Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU HP Thi, H Lee IEIE Transactions on Smart Processing and Computing 6 (3), 210-219, 2017 | | 2017 |
| Low latency check node unit architecture for nonbinary LDPC decoding HP Thi, H Lee 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 400-401, 2016 | | 2016 |
| Efficient Parallel Block-Layered Nonbinary LDPC Decoding on a GPU HP Thi, S Ajaz, H Lee | | |
