| Software transactional memory: Why is it only a research toy? C Cascaval, C Blundell, M Michael, HW Cain, P Wu, S Chiras, ... Communications of the ACM 51 (11), 40-46, 2008 | 430 | 2008 |
| An architectural evaluation of Java TPC-W HW Cain, R Rajwar, M Marden, MH Lipasti Proceedings HPCA Seventh International Symposium on High-Performance …, 2001 | 189 | 2001 |
| Robust architectural support for transactional memory in the power architecture HW Cain, MM Michael, B Frey, C May, D Williams, H Le ACM SIGARCH Computer Architecture News 41 (3), 225-236, 2013 | 169 | 2013 |
| Accurate, efficient, and adaptive calling context profiling X Zhuang, MJ Serrano, HW Cain, JD Choi Proceedings of the 27th ACM SIGPLAN Conference on Programming Language …, 2006 | 149 | 2006 |
| Precise and accurate processor simulation HW Cain, KM Lepak, BA Schwartz, MH Lipasti Workshop on Computer Architecture Evaluation using Commercial Workloads, HPCA 8, 2002 | 132 | 2002 |
| Memory ordering: A value-based approach HW Cain, MH Lipasti ACM SIGARCH Computer Architecture News 32 (2), 90, 2004 | 115 | 2004 |
| Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing MMK Martin, DJ Sorin, HW Cain, MD Hill, MH Lipasti Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001 | 88 | 2001 |
| Mechanism for data cache replacement based on region policies HW Cain, JD Choi, P Pattnaik, MJ Serrano US Patent 7,793,049, 2010 | 59 | 2010 |
| Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions CM Barton, HW Cain III, BG Frey, HQ Le, MM Michael, RE Silvera, ... US Patent App. 13/176,833, 2013 | 51 | 2013 |
| Characterizing a Java implementation of TPC-W T Bezenek, T Cain, R Dickson, T Heil, M Martin, C McCurdy, R Rajwar, ... Third Workshop On Computer Architecture Evaluation Using Commercial Workloads, 2000 | 51 | 2000 |
| A callgraph-based search strategy for automated performance diagnosis HW Cain, BP Miller, BJN Wylie European Conference on Parallel Processing, 108-122, 2000 | 47 | 2000 |
| Verifying sequential consistency using vector clocks HW Cain, MH Lipasti Proceedings of the fourteenth annual ACM symposium on Parallel algorithms …, 2002 | 45 | 2002 |
| Redeeming ipc as a performance metric for multithreaded programs KM Lepak, HW Cain, MH Lipasti 2003 12th International Conference on Parallel Architectures and Compilation …, 2003 | 40 | 2003 |
| Load value prediction via path-based address prediction: Avoiding mispredictions due to conflicting stores R Sheikh, HW Cain, R Damodaran Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 39 | 2017 |
| Compiler and runtime techniques for software transactional memory optimization P Wu, MM Michael, C von Praun, T Nakaike, R Bordawekar, HW Cain, ... Concurrency and Computation: Practice and Experience 21 (1), 7-23, 2009 | 39 | 2009 |
| Conditional memory ordering C Von Praun, HW Cain, JD Choi, KD Ryu ACM SIGARCH Computer Architecture News 34 (2), 41-52, 2006 | 39 | 2006 |
| Cache restoration for highly partitioned virtualized systems D Daly, HW Cain IEEE International Symposium on High-Performance Comp Architecture, 1-10, 2012 | 27 | 2012 |
| Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor HW Cain, P Nagpurkar 2010 IEEE International Symposium on Performance Analysis of Systems …, 2010 | 25 | 2010 |
| Hypercriticality MY Vardi Communications of the ACM 53 (7), 5-5, 2010 | 23* | 2010 |
| Constraint Graph Analysis of Multithreaded Programs. HW Cain, MH Lipasti, R Nair IEEE PACT, 4-14, 2003 | 23 | 2003 |
Mikko LipastiProfessor, Electrical and Computer Engineering, University of Wisconsin-MadisonVahvistettu sähköpostiosoite verkkotunnuksessa engr.wisc.edu
