| A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing Y Van De Burgt, E Lubberman, EJ Fuller, ST Keene, GC Faria, S Agarwal, ... Nature materials 16 (4), 414-418, 2017 | 1662 | 2017 |
| Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing EJ Fuller, ST Keene, A Melianas, Z Wang, S Agarwal, Y Li, Y Tuchman, ... Science 364 (6440), 570-574, 2019 | 680 | 2019 |
| Li-ion synaptic transistor for low power analog computing EJ Fuller, FE Gabaly, F Léonard, S Agarwal, SJ Plimpton, ... Advanced Materials 29 (SAND-2017-0895J), 2016 | 580 | 2016 |
| Resistive memory device requirements for a neural algorithm accelerator S Agarwal, SJ Plimpton, DR Hughart, AH Hsia, I Richter, JA Cox, ... 2016 International Joint Conference on Neural Networks (IJCNN), 929-938, 2016 | 217 | 2016 |
| Analog architectures for neural network acceleration based on non-volatile memory TP Xiao, CH Bennett, B Feinberg, S Agarwal, MJ Marinella Applied Physics Reviews 7 (3), 2020 | 204 | 2020 |
| Multiscale co-design analysis of energy, latency, area, and accuracy of a ReRAM analog neural training accelerator MJ Marinella, S Agarwal, A Hsia, I Richter, R Jacobs-Gedrim, J Niroula, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1 …, 2018 | 198 | 2018 |
| Tunnel field effect transistor with raised germanium source SH Kim, S Agarwal, ZA Jacobson, P Matheu, C Hu, TJK Liu IEEE electron device letters 31 (10), 1107-1109, 2010 | 175 | 2010 |
| Energy scaling advantages of resistive memory crossbar based computation and its application to sparse coding S Agarwal, TT Quach, O Parekh, AH Hsia, EP DeBenedictis, CD James, ... Frontiers in neuroscience 9, 484, 2016 | 126 | 2016 |
| Band-edge steepness obtained from Esaki/backward diode current–voltage characteristics S Agarwal, E Yablonovitch IEEE Transactions on Electron Devices 61 (5), 1488-1493, 2014 | 101 | 2014 |
| Panther: A programmable architecture for neural network training harnessing energy-efficient reram A Ankit, I El Hajj, SR Chalamalasetti, S Agarwal, M Marinella, M Foltin, ... IEEE Transactions on Computers 69 (8), 1128-1142, 2020 | 100 | 2020 |
| Low-Voltage, CMOS-Free Synaptic Memory Based on LiXTiO2 Redox Transistors Y Li, EJ Fuller, S Asapu, S Agarwal, T Kurita, JJ Yang, AA Talin ACS applied materials & interfaces 11 (42), 38982-38992, 2019 | 99 | 2019 |
| Engineering the electron–hole bilayer tunneling field-effect transistor S Agarwal, JT Teherani, JL Hoyt, DA Antoniadis, E Yablonovitch IEEE Transactions on Electron Devices 61 (5), 1599-1606, 2014 | 70 | 2014 |
| Achieving ideal accuracies in analog neuromorphic computing using periodic carry S Agarwal, RBJ Gedrim, AH Hsia, DR Hughart, EJ Fuller, AA Talin, ... 2017 Symposium on VLSI Technology, T174-T175, 2017 | 66 | 2017 |
| Data-driven discovery and synthesis of high entropy alloy hydrides with targeted thermodynamic stability M Witman, G Ek, S Ling, J Chames, S Agarwal, J Wong, MD Allendorf, ... Chemistry of Materials 33 (11), 4067-4076, 2021 | 61 | 2021 |
| Designing a low-voltage, high-current tunneling transistor Sapan Agarwal and Eli Yablonovitch Introduction Tunneling field effect transistors (TFETs) have the potential to … S Agarwal CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, 79, 2015 | 60* | 2015 |
| Extracting an empirical intermetallic hydride design principle from limited data via interpretable machine learning M Witman, S Ling, DM Grant, GS Walker, S Agarwal, V Stavila, ... The Journal of Physical Chemistry Letters 11 (1), 40-47, 2019 | 58 | 2019 |
| Redox transistors for neuromorphic computing EJ Fuller, Y Li, C Bennet, ST Keene, A Melianas, S Agarwal, MJ Marinella, ... IBM Journal of Research and Development 63 (6), 9: 1-9: 9, 2019 | 46 | 2019 |
| Using floating-gate memory to train ideal accuracy neural networks S Agarwal, D Garland, J Niroula, RB Jacobs-Gedrim, A Hsia, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …, 2019 | 45 | 2019 |
| Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on S Agarwal, E Yablonovitch 69th Device Research Conference, 199-200, 2011 | 45 | 2011 |
| On the accuracy of analog neural network inference accelerators TP Xiao, B Feinberg, CH Bennett, V Prabhakar, P Saxena, V Agrawal, ... IEEE Circuits and Systems Magazine 22 (4), 26-48, 2022 | 44 | 2022 |
Matthew J MarinellaArizona State UniversityVahvistettu sähköpostiosoite verkkotunnuksessa asu.edu
