| Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits K Roy, S Mukhopadhyay, H Mahmoodi-Meimand Proceedings of the IEEE 91 (2), 305-327, 2003 | 3199 | 2003 |
| Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS S Mukhopadhyay, H Mahmoodi, K Roy IEEE transactions on computer-aided design of integrated circuits and …, 2005 | 608 | 2005 |
| A process-tolerant cache architecture for improved yield in nanoscale technologies A Agarwal, BC Paul, H Mahmoodi, A Datta, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (1), 27-38, 2005 | 269 | 2005 |
| Ultra low-power clocking scheme using energy recovery and clock gating H Mahmoodi, V Tirumalashetty, M Cooke, K Roy IEEE transactions on very large scale integration (VLSI) systems 17 (1), 33-44, 2008 | 237 | 2008 |
| Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style H Mahmoodi-Meimand, K Roy IEEE Transactions on Circuits and Systems I: Regular Papers 51 (3), 495-503, 2004 | 206 | 2004 |
| Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits H Mahmoodi, S Mukhopadhyay, K Roy IEEE Journal of Solid-State Circuits 40 (9), 1787-1796, 2005 | 201 | 2005 |
| Statistical design and optimization of SRAM cell for yield enhancement S Mukhopadhyay, H Mahmoodi, K Roy IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 172 | 2004 |
| Low-power scan design using first-level supply gating S Bhunia, H Mahmoodi, D Ghosh, S Mukhopadhyay, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 384-395, 2005 | 165 | 2005 |
| Computation sharing programmable FIR filter for low-power and high-performance applications J Park, W Jeong, H Mahmoodi-Meimand, Y Wang, H Choo, K Roy IEEE Journal of solid-state Circuits 39 (2), 348-357, 2004 | 150 | 2004 |
| Modeling and circuit synthesis for independently controlled double gate FinFET devices A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy IEEE Transactions on Computer-aided Design of Integrated circuits and …, 2007 | 118 | 2007 |
| Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement S Mukhopadhyay, H Mahmoodi-Meimand, K Roy 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004 | 115 | 2004 |
| A low-power SRAM using bit-line charge-recycling K Kim, H Mahmoodi, K Roy IEEE journal of solid-state circuits 43 (2), 446-459, 2008 | 111 | 2008 |
| Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS S Mukhopadhyay, K Kim, H Mahmoodi, K Roy IEEE Journal of Solid-State Circuits 42 (6), 1370-1382, 2007 | 94 | 2007 |
| Double-gate SOI devices for low-power and high-performance applications K Roy, H Mahmoodi, S Mukhopadhyay, H Ananthan, A Bansal, T Cakici ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 92 | 2005 |
| Asymmetrically doped FinFETs for low-power robust SRAMs F Moradi, SK Gupta, G Panagopoulos, DT Wisland, H Mahmoodi, K Roy IEEE transactions on electron devices 58 (12), 4241-4249, 2011 | 88 | 2011 |
| Domino logic designs for high-performance and leakage-tolerant applications F Moradi, TV Cao, EI Vatajelu, A Peiravi, H Mahmoodi, DT Wisland Integration 46 (3), 247-254, 2013 | 79 | 2013 |
| Data-retention flip-flops for power-down applications H Mahmoodi-Meimand, K Roy 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 72 | 2004 |
| Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS Q Chen, H Mahmoodi, S Bhunia, K Roy 23rd IEEE VLSI Test Symposium (VTS'05), 292-297, 2005 | 71 | 2005 |
| Security and complexity analysis of LUT-based obfuscation: From blueprint to reality G Kolhe, HM Kamali, M Naicker, TD Sheaves, H Mahmoodi, PDS Manoj, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 67 | 2019 |
| Hybrid STT-CMOS designs for reverse-engineering prevention T Winograd, H Salmani, H Mahmoodi, K Gaj, H Homayoun Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 67 | 2016 |
