Residue-to-binary arithmetic converter for the moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) AA Hiasat, SH Abdel-Aty-Zohdy
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1998
137 1998 New efficient memoryless residue to binary converter ASA Hiasat
IEEE Trasnsactions on Circuits and System 35, 1441-1444, 1988
137 * 1988 High-speed and reduced-area modular adder structures for RNS AA Hiasat
IEEE Transactions on Computers 51 (1), 84-89, 2002
128 2002 New efficient structure for a modular multiplier for RNS AA Hiasat
IEEE Transactions on Computers 49 (2), 170-174, 2000
92 2000 A Memoryless mod (2<sup>n</sup>±1) Residue Multiplier A Hiasat
Electronics Letters 28, 414-415, 1991
82 * 1991 VLSI implementation of new arithmetic residue to binary decoders AA Hiasat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (1), 153-158, 2005
77 2005 Design and implementation of a new efficient median filtering algorithm AA Hiasat, MM Al-Ibrahim, KM Gharaibeh
IEE Proceedings-Vision, Image and Signal Processing 146 (5), 273-278, 1999
35 1999 A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set A Hiasat
IEEE Transactions on Circuits and Systems I: Regular Papers, 1-11, 2016
31 2016 Residue Number System to Binary Converter for the Moduli Set (2^n-1, 2^{n-1}, 2^n+1) AHA Sweidan
Journal of Systems Architecture 49 (1-2), 53-58, 2003
31 2003 Design and implementation of an RNS division algorithm AA Hiasat, HS Abdel-Aty-Zohdy
Proceedings 13th IEEE Sympsoium on Computer Arithmetic, 240-249, 1997
31 1997 An Efficient Reverse Converter for the Three-Moduli Set (2n+1 1; 2n; 2n 1) A Hiasat
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016
29 2016 Efficient RNS Scalers for the Extended Three-Moduli Set A Hiasat
IEEE Transactions on Computers 66 (7), 1253-1260, 2017
27 2017 Semi-custom VLSI design and implementation of a new efficient RNS division algorithm AA Hiasat, H Abdel-Aty-Zohdy
The Computer Journal 42 (3), 232-240, 1999
26 1999 A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n − (2p ± 1)) AA Hiasat
The Computer Journal 47 (1), 93-102, 2004
24 2004 Combinational logic approach for implementing an improved approximate squaring function AA Hiasat, HS Abdel-Aty-Zohdy
IEEE Journal of Solid-state Circuits 34 (2), 236-240, 1999
24 1999 A Residue-to-Binary Converter for the Extended Four-Moduli Set A Hiasat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017
23 2017 Residue-to-binary decoder for an enhanced moduli set A Hiasat, A Swiedan
IEE Proceedings - Computers and Digital Techniques 151 (2), 127-130, 2004
20 2004 Bit-serial architecture for rank order and stack filters A Hiasat, O Hasan
Integration 36 (1-2), 3-12, 2003
20 2003 A high-speed division algorithm for residue number system AA Hiasat, HS Abdel-Aty-Zohdy
Proceedings of ISCAS'95-International Symposium on Circuits and Systems 3 …, 1995
20 1995 RNS arithmetic multiplier for medium and large moduli AA Hiasat
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002
19 2002 
Hoda Abdel-Aty-ZohdyOakland UniversityAdresse e-mail validée de oakland.edu