| 29.7 A 2.5GHz injection-locked ADPLL with 197fsrmsintegrated jitter and −65dBc reference spur using time-division dual calibration S Kim, HG Ko, SY Cho, J Lee, S Shin, MS Choo, H Chi, DK Jeong 2017 IEEE International Solid-State Circuits Conference (ISSCC), 494-495, 2017 | 38 | 2017 |
| A 4–20-Gb/s 1.87-pJ/b continuous-rate digital CDR circuit with unlimited frequency acquisition capability in 65-nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong IEEE Journal of Solid-State Circuits 56 (5), 1597-1607, 2020 | 35 | 2020 |
| A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection SY Cho, S Kim, MS Choo, HG Ko, J Lee, W Bae, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2691-2702, 2018 | 29 | 2018 |
| A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection SY Cho, S Kim, MS Choo, J Lee, HG Ko, S Jang, SH Chu, W Bae, Y Kim, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 26 | 2015 |
| 27.7 A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time M Choi, CH Kye, J Oh, MS Choo, DK Jeong 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 432-434, 2019 | 17 | 2019 |
| An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter MS Choo, HG Ko, SY Cho, K Lee, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1819-1823, 2018 | 15 | 2018 |
| A 15-GHz, 17.8-mW, 213-fs injection-locked PLL with maximized injection strength using adjustment of phase domain response MS Choo, Y Song, SY Cho, HG Ko, K Park, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 66 (12), 1932-1936, 2019 | 10 | 2019 |
| A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS K Park, K Lee, SY Cho, J Lee, J Hwang, MS Choo, DK Jeong 2019 Symposium on VLSI Circuits, C194-C195, 2019 | 9 | 2019 |
| A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel K Park, J Lee, K Lee, MS Choo, S Jang, SH Chu, S Kim, DK Jeong IEEE Transactions on Circuits and Systems II: Express Briefs 64 (12), 1432-1436, 2017 | 7 | 2017 |
| A PVT variation-robust all-digital injection-locked clock multiplier with real-time offset tracking using time-division dual calibration MS Choo, S Kim, HG Ko, SY Cho, K Park, J Lee, S Shin, H Chi, DK Jeong IEEE Journal of Solid-State Circuits 56 (8), 2525-2538, 2021 | 6 | 2021 |
| A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology MS Choo, K Park, HG Ko, SY Cho, K Lee, DK Jeong IEEE Journal of Solid-State Circuits 54 (10), 2812-2822, 2019 | 5 | 2019 |
| A current-mode digital AOT 4-phase buck voltage regulator M Choi, CH Kye, J Oh, MS Choo, DK Jeong IEEE Solid-State Circuits Letters 2 (11), 244-247, 2019 | 5 | 2019 |
| A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique S Kim, S Jang, SY Cho, MS Choo, GS Jeong, W Bae, DK Jeong Journal of semiconductor technology and science 16 (6), 860-866, 2016 | 4 | 2016 |
| An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies D Lee, G Park, J Han, MS Choo IEEE Access 11, 7530-7539, 2022 | 3 | 2022 |
| A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop MS Choo, HG Ko, SY Cho, K Lee, DK Jeong 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 73-76, 2018 | 3 | 2018 |
| A− 247.1 dB FoM,− 77.9 dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration Y Song, K Ha, HG Ko, MS Choo, DK Jeong ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 2 | 2022 |
| Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter IW Jang, MS Choo 2023 International Conference on Electronics, Information, and Communication …, 2023 | 1 | 2023 |
| Improving mask yield by implementing an advanced mask blank inspection system G Inderhees, B Kalsbeck, A Tan, P Chung, JU Hur, E Kwon, M Choo, ... Photomask Technology 2018 10810, 150-159, 2018 | 1 | 2018 |
| A theoretical analysis of phase shift in pulse injection-locked oscillators J Lee, S Kim, MS Choo, SY Cho, HG Ko, DK Jeong 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1662-1665, 2016 | 1 | 2016 |
| A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology HS Choi, JG Lee, KH Lee, D Koh, JW Sull, HR Do, CH Kye, DK Jeong, ... 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2024 | | 2024 |
Deog-Kyoon JeongSeoul National University, Department of Electrical and Computer EngineeringAdresse e-mail validée de snu.ac.kr