2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2 /HfO2 Stacked Gate-Oxide Structure S Kumar, E Goel, K Singh, B Singh, PK Singh, K Baral, S Jit
IEEE Transactions on Electron Devices 64 (3), 960-968, 2017
181 2017 A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO2 /High- S Kumar, E Goel, K Singh, B Singh, M Kumar, S Jit
IEEE Transactions on Electron Devices 63 (8), 3291-3299, 2016
152 2016 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs E Goel, S Kumar, K Singh, B Singh, M Kumar, S Jit
IEEE Transactions on Electron Devices 63 (3), 966-973, 2016
119 2016 Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
IEEE Transactions on Electron Devices 63 (6), 2299-2305, 2016
78 2016 2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO2 /HfO2 Stacked Gate-Oxide Structure S Kumar, K Singh, S Chander, E Goel, PK Singh, K Baral, B Singh, S Jit
IEEE Transactions on Electron Devices 65 (1), 331-338, 2017
71 2017 Temperature analysis of Ge/Si heterojunction SOI-tunnel FET S Chander, SK Sinha, S Kumar, PK Singh, K Baral, K Singh, S Jit
Superlattices and Microstructures 110, 162-170, 2017
63 2017 2-D analytical threshold voltage model for dielectric pocket double-gate junctionless FETs by considering source/drain depletion effect B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
IEEE Transactions on Electron Devices 64 (3), 901-908, 2017
44 2017 Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications B Singh, D Gola, E Goel, S Kumar, K Singh, S Jit
Journal of Computational Electronics 15 (2), 502-507, 2016
44 2016 Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs PK Tiwari, S Dubey, K Singh, S Jit
Superlattices and Microstructures 51 (5), 715-724, 2012
30 2012 Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs N Kumar, V Purwar, H Awasthi, R Gupta, K Singh, S Dubey
Microelectronics Journal 113, 105104, 2021
29 2021 Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit
Materials science in semiconductor processing 58, 82-88, 2017
28 2017 Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer J Talukdar, G Rawat, K Singh, K Mummaneni
Journal of Electronic Materials 49, 4333-4342, 2020
27 2020 Low frequency noise analysis of single gate extended source tunnel FET J Talukdar, G Rawat, K Singh, K Mummaneni
Silicon 13, 3971-3980, 2021
25 2021 Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure B Singh, TN Rai, D Gola, K Singh, E Goel, S Kumar, PK Tiwari, S Jit
Materials Science in Semiconductor Processing 71, 161-165, 2017
21 2017 Annealing-temperature effects on the properties of ZnO thin films and Pd/ZnO Schottky contacts grown on n-Si (1 0 0) substrates by vacuum deposition method AB Yadav, K Singh, A Pandey, S Jit
Superlattices and Microstructures 71, 250-260, 2014
21 2014 Device physics based analytical modeling for electrical characteristics of single gate extended source tunnel FET (SG-ESTFET) J Talukdar, G Rawat, B Choudhuri, K Singh, K Mummaneni
Superlattices and Microstructures 148, 106725, 2020
17 2020 Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs E Goel, S Kumar, B Singh, K Singh, S Jit
Superlattices and Microstructures 106, 147-155, 2017
15 2017 A compact 2-D analytical model for electrical characteristics of double-gate Tunnel-FETs with a SiO2/High-k stacked gate-oxide structure S Kumar, E Goel, K Singh, B Singh, M Kumar, S Jit
IEEE Trans. Electron Devices 60, 3291-3299, 2016
14 2016 Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs E Goel, B Singh, S Kumar, K Singh, S Jit
Indian Journal of Physics 91, 383-390, 2017
13 2017 Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs V Purwar, R Gupta, N Kumar, H Awasthi, VK Dixit, K Singh, S Dubey, ...
Applied Physics A 126, 1-8, 2020
12 2020 
Satyabrata JitIndian Institute of Technology (Banaras Hindu University) Varanasi, IndiaAdresse e-mail validée de iitbhu.ac.in