Chipmunk: A systolically scalable 0.9 mm2 , 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference F Conti, L Cavigelli, G Paulin, I Susmelj, L Benini
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018
55 2018 22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing F Conti, D Rossi, G Paulin, A Garofalo, A Di Mauro, G Rutishauer, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 21-23, 2023
25 2023 Marsellus: A heterogeneous RISC-V AI-IoT end-node SoC with 2–8 b DNN acceleration and 30%-boost adaptive body biasing F Conti, G Paulin, A Garofalo, D Rossi, A Di Mauro, G Rutishauser, ...
IEEE Journal of Solid-State Circuits 59 (1), 128-142, 2023
19 2023 MiniFloat-NN and ExSdotp: An ISA extension and a modular open hardware unit for low-precision training on RISC-V cores L Bertaccini, G Paulin, T Fischer, S Mach, L Benini
2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), 1-8, 2022
15 2022 Ita: An energy-efficient attention and softmax accelerator for quantized transformers G Islamoglu, M Scherer, G Paulin, T Fischer, VJB Jung, A Garofalo, ...
2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023
11 2023 RNN-based radio resource management on multicore RISC-V accelerator architectures G Paulin, R Andri, F Conti, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (9 …, 2021
10 2021 Vau da muntanialas: Energy-efficient multi-die scalable acceleration of RNN inference G Paulin, F Conti, L Cavigelli, L Benini
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (1), 244-257, 2021
9 2021 Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters G Paulin, M Cavalcante, P Scheffler, L Bertaccini, Y Zhang, F Gürkaynak, ...
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 44-49, 2022
8 2022 Occamy: A 432-core 28.1 DP-GFLOP/s/W 83% FPU utilization dual-chiplet, dual-HBM2E RISC-V-based accelerator for stencil and sparse linear algebra computations with 8-to-64-bit … G Paulin, P Scheffler, T Benz, M Cavalcante, T Fischer, M Eggimann, ...
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2024
7 2024 MiniFloats on RISC-V cores: ISA extensions with mixed-precision short dot products L Bertaccini, G Paulin, M Cavalcante, T Fischer, S Mach, L Benini
IEEE Transactions on Emerging Topics in Computing, 2024
5 2024 CONVOLVE: Smart and seamless design of smart edge processors M Gomony, F Putter, A Gebregiorgis, G Paulin, L Mei, V Jain, S Hamdioui, ...
arXiv preprint arXiv:2212.00873, 2022
3 2022 Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET P Scheffler, T Benz, V Potocnik, T Fischer, L Colagrande, N Wistoff, ...
IEEE Journal of Solid-State Circuits, 2025
1 2025 PetaOps/W edge-AI MD Gomony, F De Putter, A Gebregiorgis, G Paulin, L Mei, V Jain, ...
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
1 2023 Multi-System GNSS Receiver Software G Paulin
Technical report, Distributed Computing Group Computer Engineering and …, 2017
1 2017 Key Technologies and Design Aspects for Wafer Level Packaging of High Performance Computing Modules K Zoschke, H Oppermann, M Schiffer, I Ndip, KF Becker, M Adler, ...
2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 433-440, 2024
2024 Hardware Architectures for Energy-Efficient Neural Network Acceleration G Paulin
ETH Zurich, 2023
2023 
Luca BeniniETH Zürich, Università di BolognaAdresse e-mail validée de unibo.it