Matthias Jung

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Norbert WehnUniversity of KaiserslauternAdresse e-mail validée de eit.uni-kl.de
Christian WeisUniversity of KaiserslauternAdresse e-mail validée de weiscon.de
Deepak M MathewUniversity of KaiserslauternAdresse e-mail validée de eit.uni-kl.de
Chirag SudarshanPost-Doc, Forschungszentrum JülichAdresse e-mail validée de fz-juelich.de
Lukas SteinerTechnische Universität KaiserslauternAdresse e-mail validée de eit.uni-kl.de
Kira KraftUniversity of KaiserslauternAdresse e-mail validée de eit.uni-kl.de
mohammadsadegh sadriPost-doctoral Researcher, TU KaiserslauternAdresse e-mail validée de eit.uni-kl.de
Karthik ChandrasekarNvidia (Previously @ Qualcomm and TU Delft)Adresse e-mail validée de nvidia.com
Sven GoossensIntrinsic IDAdresse e-mail validée de intrinsic-id.com
Jan LappasPHD-Student ,Microelectronic Systems Design Research Group, University of Kaiserslautern LandauAdresse e-mail validée de rptu.de
Sven KrumkeProfessor of Mathematics, University of KaiserslauternAdresse e-mail validée de mathematik.uni-kl.de
Benny ÅkessonSenior Research Fellow, TNO-ESI | Endowed Professor, University of AmsterdamAdresse e-mail validée de tno.nl
Ahmed HemaniKTH Royal Institute of Technology, StockholmAdresse e-mail validée de kth.se
Jasmin JahicResearcher, University of CambridgeAdresse e-mail validée de cam.ac.uk
Muhammad Mohsin GhaffarTU KaiserslauternAdresse e-mail validée de eit.uni-kl.de
Luca BeniniETH Zürich, Università di BolognaAdresse e-mail validée de unibo.it
Christian MenardChair for Compiler Construction, TU DresdenAdresse e-mail validée de tu-dresden.de
Taha SolimanRobert Bosch GmbHAdresse e-mail validée de de.bosch.com
Cristiano SantosUniversidade Federal do Rio Grande do SulAdresse e-mail validée de inf.ufrgs.br
Christian De SchryverRPTU Kaiserslautern-LandauAdresse e-mail validée de rptu.de

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Matthias Jung

University of Würzburg, Fraunhofer IESE

Adresse e-mail validée de uni-wuerzburg.de - Page d'accueil

Embedded Systems TLM SystemC DRAM Memory Systems


Titre Trier par citations Trier par année Trier par titre	Citée par Citée par	Année
The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020	341	2020
DRAMPower: Open-source DRAM Power & Energy Estimation Tool K Chandrasekar, C Weis, Y Li, S Goossens, M Jung, O Naji, B Akesson, ... http://www.drampower.info, 2014	218	2014
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework M Jung, C Weis, N Wehn IPSJ Transactions on System LSI Design Methodology 8, 63-74, 2015	77	2015
System Simulation with gem5 and SystemC: The Keystone for Full Interoperability C Menard, M Jung, J Castrillon, N Wehn IEEE International Conference on Embedded Computer Systems Architectures …, 2017	61	2017
Approximate Computing with Partially Unreliable Dynamic Random Access Memory: Approximate DRAM M Jung, DM Mathew, C Weis, N Wehn Design Automation Conference (DAC), 2016	59	2016
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs M Jung, É Zulian, DM Mathew, M Herrmann, C Brugger, C Weis, N Wehn International Symposium On Memory Systems (MEMSYS '15), 85-91, 2015	58	2015
TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems: a Virtual Platform for Memory Controller Design Space Exploration M Jung, C Weis, N Wehn, K Chandrasekar Workshop on Rapid Simulation and Performance Evaluation 2013 (RAPIDO) HiPEAC …, 2013	52	2013
Reverse Engineering of DRAMs: Row Hammer with Crosshair M Jung, C Rheinländer, C Weis, N Wehn International Symposium on Memory Systems (MEMSYS 2016), 2016	43	2016
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs C Weis, M Jung, P Ehses, C Santos, S Pascal Vivet, Goossens, ... Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015	38	2015
Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-Wise Refresh M Sadri, M Jung, C Weis, N Wehn, L Benini Proceedings of the conference on Design, Automation & Test in Europe, 281, 2014	38	2014
DRAMSys4. 0: a fast and cycle-accurate systemC/TLM-based DRAM simulator L Steiner, M Jung, FS Prado, K Bykov, N Wehn Embedded Computer Systems: Architectures, Modeling, and Simulation: 20th …, 2020	34	2020
A Platform to Analyze DDR3 DRAM's Power and Retention Time M Jung, DM Mathew, CC Rheinlander, C Weis, N Wehn IEEE Design & Test, 2017	33	2017
A high-level DRAM timing, power and area exploration tool O Naji, C Weis, M Jung, N Wehn, A Hansson 2015 International conference on embedded computer systems: architectures …, 2015	33	2015
Driving Into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving M Jung, SA McKee, C Sudarshan, C Dropmann, C Weis, N Wehn International Symposium on Memory Systems (MEMSYS), 2018	32	2018
Exploring System Performance using Elastic Traces: Fast, Accurate and Portable R Jagtap, S Diestelhorst, A Hansson, M Jung, N Wehn IEEE International Conference on Embedded Computer Systems Architectures …, 2016	32	2016
Efficient Reliability Management in SoCs - An Approximate DRAM Perspective M Jung, DM Mathew, C Weis, N Wehn 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016	32	2016
ConGen: An Application Specific DRAM Memory Controller Generator M Jung, I Heinrich, M Natale, DM Mathew, C Weis, S Krumke, N Wehn International Symposium on Memory Systems (MEMSYS 2016), 2016	31	2016
Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs M Jung, M Sadri, C Weis, N Wehn, L Benini IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2014	26	2014
A lean, low power, low latency DRAM memory controller for transprecision computing C Sudarshan, J Lappas, C Weis, DM Mathew, M Jung, N Wehn Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th …, 2019	23	2019
DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool C Weis, A Mutaal, O Naji, M Jung, A Hansson, N Wehn International Journal of Parallel Programming (IJPP), 2016	23	2016

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