| FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework A Rodríguez, J Valverde, J Portilla, A Otero, T Riesgo, E De la Torre Sensors 18 (6), 1877, 2018 | 106 | 2018 |
| Using SRAM based FPGAs for power-aware high performance wireless sensor networks J Valverde, A Otero, M Lopez, J Portilla, E de la Torre, T Riesgo Sensors 12 (3), 2667-2692, 2012 | 76 | 2012 |
| Self-reconfigurable evolvable hardware system for adaptive image processing R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina IEEE transactions on computers 62 (8), 1481-1493, 2013 | 73 | 2013 |
| Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ... International Journal of Distributed Sensor Networks 2010, 2010 | 68 | 2010 |
| Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference …, 2011 | 61 | 2011 |
| A machine-learning-based distributed system for fault diagnosis with scalable detection quality in industrial IoT R Marino, C Wisultschew, A Otero, JM Lanza-Gutierrez, J Portilla, ... IEEE Internet of Things Journal 8 (6), 4339-4352, 2020 | 48 | 2020 |
| Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012 | 46 | 2012 |
| Run-time reconfigurable MPSoC-based on-board processor for vision-based space navigation A Pérez, A Rodríguez, A Otero, DG Arjona, A Jiménez-Peralo, ... IEEE Access 8, 59891-59905, 2020 | 41 | 2020 |
| Automatic generation of identical routing pairs for FPGA implemented DPL logic W He, A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012 | 33 | 2012 |
| IMPRESS: automated tool for the implementation of highly flexible partial reconfigurable systems with Xilinx Vivado R Zamacola, AG Martínez, J Mora, A Otero, E de La Torre 2018 International Conference on ReConFigurable Computing and FPGAs …, 2018 | 32 | 2018 |
| A Modular Peripheral to Support Self-Reconfiguration in SoCs A Otero, Á Morales-Cas, J Portilla, E de la Torre, T Riesgo Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th …, 2010 | 30 | 2010 |
| A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on, 336-343, 2011 | 27 | 2011 |
| Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on, 184-191, 2011 | 22 | 2011 |
| A novel FPGA-based evolvable hardware system based on multiple processing arrays Á Gallego, J Mora, A Otero, R Salvador, E de la Torre, T Riesgo 2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013 | 20 | 2013 |
| Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina Field Programmable Logic and Applications (FPL), 2012 22nd International …, 2012 | 19 | 2012 |
| Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems A Pérez, L Suriano, A Otero, E de la Torre 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 40-47, 2017 | 16 | 2017 |
| A scalable evolvable hardware processing array A Gallego, J Mora, A Otero, E de la Torre, T Riesgo 2013 International Conference on Reconfigurable Computing and FPGAs …, 2013 | 16 | 2013 |
| Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs J Mora, A Otero, E de la Torre, T Riesgo 2015 10th International Symposium on Reconfigurable Communication-centric …, 2015 | 15 | 2015 |
| Run-time scalable systolic coprocessors for flexible multimedia SoPCs A Otero, E de la Torre, T Riesgo, YE Krasteva 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 15 | 2010 |
| On the automatic integration of hardware accelerators into FPGA-based embedded systems C Pilato, A Cazzaniga, G Durelli, A Otero, D Sciuto, MD Santambrogio 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 14 | 2012 |
Eduardo de la TorreUniversidad Politécnica de MadridAdresse e-mail validée de upm.es
