A configurable floating-point multiple-precision processing element for HPC and AI converged computing W Mao, K Li, Q Cheng, L Dai, B Li, X Xie, H Li, L Lin, H Yu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (2), 213-226, 2021
27 2021 A high performance multi-bit-width booth vector systolic accelerator for NAS optimized deep learning neural networks M Huang, Y Liu, C Man, K Li, Q Cheng, W Mao, H Yu
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (9), 3619-3631, 2022
25 2022 Reliability exploration of system-on-chip with multi-bit-width accelerator for multi-precision deep neural networks Q Cheng, M Huang, C Man, A Shen, L Dai, H Yu, M Hashimoto
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (10), 3978-3991, 2023
12 2023 An energy-efficient mixed-bitwidth systolic accelerator for NAS-optimized deep neural networks W Mao, L Dai, K Li, Q Cheng, Y Wang, L Du, S Luo, M Huang, H Yu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (12 …, 2022
10 2022 Agile hardware and software co-design for risc-v-based multi-precision deep learning microprocessor Z He, A Shen, Q Li, Q Cheng, H Yu
Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023
8 2023 An energy-efficient bit-split-and-combination systolic accelerator for nas-based multi-precision convolution neural networks L Dai, Q Cheng, Y Wang, G Huang, J Zhou, K Li, W Mao, H Yu
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 448-453, 2022
6 2022 A low-power sparse convolutional neural network accelerator with pre-encoding radix-4 booth multiplier Q Cheng, L Dai, M Huang, A Shen, W Mao, M Hashimoto, H Yu
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (6), 2246-2250, 2022
4 2022 Multiple-precision floating-point dot product unit for efficient convolution computation K Li, W Mao, X Xie, Q Cheng, H Xie, Z Dong, H Yu
2021 IEEE 3rd International Conference on Artificial Intelligence Circuits …, 2021
3 2021 Disturbance signal recognition using convolutional neural network for DAS system Q Cheng, Y Yang, X Gui
2021 13th International Conference on Measuring Technology and Mechatronics …, 2021
3 2021 A high throughput multi-bit-width 3d systolic accelerator for nas optimized deep neural networks on fpga M Huang, Y Liu, Q Cheng, S Yang, K Li, J Luo, Z Yang, Q Li, H Yu, C Man
Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022
2 2022 A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity W Mao, D Liu, H Zhou, F Li, K Li, Q Wu, J Yang, Q Cheng, L Zhang, H Yu
IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
1 2024 How accurately can soft error impact be estimated in black-box/white-box cases?--a case study with an edge AI SoC-- Q Cheng, Q Li, L Lin, W Liao, L Dai, H Yu, M Hashimoto
Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024
1 2024 An 88.5 fs Y Liang, W Jin, Z Fang, Q Cheng, M Hashimoto
IEEE Transactions on Circuits and Systems I: Regular Papers, 2024
2024 A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping Q Cheng, L Lin, M Huang, Q Li, Z Yang, L Dai, H Yu, YJ Chen, Y Shi, ...
2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2024
2024 S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators M Zhang, Q Cheng, H Awano, L Lin, M Hashimoto
2024 IEEE 42nd International Conference on Computer Design (ICCD), 16-23, 2024
2024 
Hao Yu （余浩）SUSTech（南方科技大学）Adresse e-mail validée de sustech.edu.cn