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Jiang Gong
Jiang Gong
UESTC(Shenzhen)
Adresse e-mail validée de uestc.edu.cn - Page d'accueil
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Benefits and challenges of designing cryogenic CMOS RF circuits for quantum computers
M Mehrpoo, B Patra, J Gong, JPG van Dijk, H Homulle, G Kiene, ...
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
592019
19.3 A 200dB FoM 4-to-5GHz cryogenic oscillator with an automatic common-mode resonance calibration for quantum computing applications
J Gong, Y Chen, F Sebastiano, E Charbon, M Babaie
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 308-310, 2020
472020
A low-jitter and low-spur charge-sampling PLL
J Gong, E Charbon, F Sebastiano, M Babaie
IEEE Journal of Solid-State Circuits 57 (2), 492-504, 2021
302021
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB in 22nm FinFET
J Gong, B Patra, L Enthoven, J van Staveren, F Sebastiano, M Babaie
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
292022
A cryo-CMOS PLL for quantum computing applications
J Gong, E Charbon, F Sebastiano, M Babaie
IEEE Journal of Solid-State Circuits 58 (5), 1362-1375, 2022
202022
A 10-to-12 GHz 5 mW charge-sampling PLL achieving 50 fsec RMS jitter,-258.9 dB FOM and-65 dBc reference spur
J Gong, F Sebastiano, E Charbon, M Babaie
2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 15-18, 2020
172020
A 2.6-to-4.1 GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving-249.4 dB FoM and-59dBc Fractional Spurs
Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 380-382, 2022
162022
A 1.33 mW, 1.6psrms-Integrated-Jitter, 1.8-2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet-of-Things Applications
J Gong, Y He, A Ba, YH Liu, J Dijkhuis, S Traferro, C Bachmann, K Philips, ...
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 44-47, 2018
162018
A cryo-CMOS oscillator with an automatic common-mode resonance calibration for quantum computing applications
J Gong, Y Chen, E Charbon, F Sebastiano, M Babaie
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (12), 4810-4822, 2022
142022
A fractional-N digitally intensive PLL achieving 428-fs Jitter and<− 54-dBc spurs under 50-mVpp supply ripple
Y Chen, J Gong, RB Staszewski, M Babaie
IEEE Journal of Solid-State Circuits 57 (6), 1749-1764, 2021
142021
A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications
J Gong, E Charbon, F Sebastiano, M Babaie
2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021
132021
A low-spur fractional-N PLL based on a time-mode arithmetic unit
Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ...
IEEE Journal of Solid-State Circuits 58 (6), 1552-1571, 2022
122022
A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing
L Enthoven, J Van Staveren, J Gong, M Babaie, F Sebastiano
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
102022
A 10-Gb/s 275-fsec jitter cryo-CMOS charge-sampling CDR for quantum computing application
L De Jong, JI Bas, J Gong, F Sebastiano, M Babaie
IEEE Microwave and Wireless Technology Letters 33 (6), 875-878, 2023
32023
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